Lattice Semiconductor ispLever Core Multi-Channel DMA Controller User Manual Download Page 11

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Lattice Semiconductor

Multi-Channel DMA Controller User’s Guide

The functionality of the core in the non-8237 mode is very similar to that of the 8237 mode. However, the two
modes have totally different sets of programmable control registers. This increases the programmability features in
the non-8237 mode. Some of the features available only in the non-8237 mode are:

• Multiple channels

• Configurable channels for DMA transfers between memory-and-memory or I/O-and-memory

• Parameterized address output and data bus width

• Parameterized word-count register

The microprocessor programs a number of registers to ensure the DMA controller functions properly. The internal
registers are accessed when the

cs_n

signal is asserted and the address of the register is placed on the

ain

bus.

When the

iowin_n

signal is low, the registers are over written with the data on

dbin

bus. When the

iorin_n

sig-

nal is asserted, the registers are read and their contents are placed on the

dbout

bus. The least significant eight

bits of the data bus can access the internal registers irrespective of the data bus width.

To prevent erroneous behavior, the DMA registers should be programmed only when the controller is in the Idle
State (SI) or before it receives the

hlda

signal from the microprocessor. Not adhering to these rules will cause the

DMA controller to function in a non-deterministic way. The registers visible to the microprocessor are different for
the 8237 and non-8237 modes.

The MCDMA controller core is a fully synchronous machine that runs off the positive edge of the clock. However,
the DMA request signals,

dreq[N-1:0

], are asynchronous with respect to the clock. These signals have to be

synchronized within the core.

DMA Initialization

Once the Command and Mode registers are programmed and the controller is enabled, DMA transfers can be initi-
ated either by asserting the unmasked channel’s

dreq

signal or by requesting to DMA by programming the request

register. The internal registers of the core are accessible during the idle state (SI) when no channel is requesting
service and no DMA transfers are in progress.

The core operates in two cycles: Idle and Active. The core remains in the idle cycle as long as it is not performing
any DMA transfers and none of the unmasked channels have a pending request. In this state, the microprocessor
can program the device. Once an unmasked channel requests DMA service, the device asserts the

hreq

signal to

take control of the bus and enters the first active cycle state S0. The device can still be programmed in the S0 state
until it receives the

hlda

signal from the bus arbiter. For DMA transfers between memory and I/O, the active cycles

go from states S1 through S4. When memory-to-memory DMA transfers are performed, the active cycles go
through states S11, S12, S13, S14 for the memory read operation and states S21, S22, S23, S24 for the memory
write operation. Wait states are introduced whenever the slave device is not ready for the transfer.

MCDMA Transfer Modes

When the MCDMA is in the active cycle, the DMA service takes place in one of the following three modes:

•

Single Transfer Mode:

In single transfer mode, the device is programmed to make one transfer only. Following

each transfer, the Word Count decrements and the address decrements or increment, depending on what is
selected in the Mode register. To be recognized, the

dreq

signal must be held active until

dack

becomes active.

dreq

is held active throughout the single transfer,

hreq

goes inactive and releases the bus to the system. After

the transfer,

hreq

will go active again. When the controller receives a new

hlda