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Lattice Semiconductor ispLever Core Multi-Channel DMA Controller User Manual Download Page 6

 

Lattice Semiconductor

Multi-Channel DMA Controller User’s Guide

 

6

 

Figure 2. MCDMA Finite State Machine for 8237 and Non-8237 Modes

Request

Dropped

Illegal

Mode

Illegal

I/O Mode

(8237 only)

LAST_TRAN/

SINGLE_TRAN

Termination

LAST_TRAN/

SINGLE_TRAN

Termination

Write

Phase

Read

Phase

Another T

ransfer

Compressed

(8237 only)

NR

NR

NR

NR

NR

NR

NR

S12

SI

S0

S1/S11

S13

S14

S23

S24

S22

S21

S2

S3

S4

NR

Not Ready (NR)

No REQ

No HDLA

Not LAST_TRAN

MEM-MEM

I/O-MEM

Summary of Contents for ispLever Core Multi-Channel DMA Controller

Page 1: ...February 2006 ipug11_04 0 Multi Channel DMA Controller User s Guide ispLever CORE CORE TM...

Page 2: ...om the Intel 8237A core in the following ways The bi directional ports are split into separate input and output ports MCDMA does not support the cascade mode of operation The latch that holds the uppe...

Page 3: ...Lattice Semiconductor Multi Channel DMA Controller User s Guide 3 Software DMA requests...

Page 4: ...the data bus CPU Interface Data The CPU Interface Data block contains all the configuration registers It includes all the routing logic required to transfer either the selected register s contents du...

Page 5: ...3 S14 S21 S22 S23 and S24 If the next transfer should continue for the same request the path from S11 to S24 is repeated If memory to I O or I O to memory is enabled the FSM goes through states S2 S3...

Page 6: ...Modes Request Dropped Illegal Mode Illegal I O Mode 8237 only LAST_TRAN SINGLE_TRAN Termination LAST_TRAN SINGLE_TRAN Termination Write Phase Read Phase Another Transfer Compressed 8237 only NR NR NR...

Page 7: ...ty at that time The DMA priority scheme will be described more in the priority request encoder section Non 8237 Mode In this mode memory to memory transfer is detected if bit zero of the current chann...

Page 8: ...f the memory to memory transfer mode In the 8237 mode the content of the current address register on Channel 1 is put on the address bus In the non 8237 mode the content of the destination address reg...

Page 9: ...the DMA transfer The dack signal is asserted The dreq signal does not need to be held asserted after this state if block or single transfer mode is selected memr_n or iorout_n is asserted depending on...

Page 10: ...ns are addressable but I O locations are not addressable The source address register in the non 8237 mode holds the memory location address during DMA transfers between an I O device and memory Active...

Page 11: ...est register The internal registers of the core are accessible during the idle state SI when no channel is requesting service and no DMA transfers are in progress The core operates in two cycles Idle...

Page 12: ...e MODE_8237 Defines the DMA mode If it is TRUE the DMA will be in 8237 mode otherwise it will be in non 8237 mode TRUE FALSE Number of Channel NUM_CHANNELS Sets the number of channels In 8237 mode it...

Page 13: ...ters In the 8237 mode ain is 4 bits wide In the non 8237 mode the bus width depends on the number of channels selected dbin DATA_BUS_WIDTH 1 0 Input N A Data Bus Input The CPU writes to the internal r...

Page 14: ...n and iorin_n are asserted Clock edges 1 2 and 3 indicate the edges on which the data is valid aen Output High Address Enable This active high signal enables the 8 bit latch that contains the upper 8...

Page 15: ...Lattice Semiconductor Multi Channel DMA Controller User s Guide 15 Figure 4 Processor Read Timing Waveform Clock cs_n iorin_n ain 1 2 3 dbout...

Page 16: ...ss Si Note 1 This timing diagram demonstrates the extended write operation In the 8237 mode when normal write operation is selected iowout_n or the memw_n is asserted one clock cycle later If compress...

Page 17: ...ialization is enabled the value in the Base Word Count register is reloaded at the end of the DMA service When the value in the register goes from zero to 0xFFFF a terminal count eopout_n signal is ge...

Page 18: ...r master clear clears this register The channel must be in block mode in order to make a software request Table 10 lists the request register format in 8237 Mode Status Register This register is only...

Page 19: ...ress increment 1 Address decrement 7 6 10 Demand mode select 01 Single mode select 10 Block mode select 11 Cascade mode unsupported Bit Description 0 0 Channel 0 unmasked 1 Channel 0 masked 1 0 Channe...

Page 20: ...in consecutive cycles after clearing the byte pointer The number of cycles taken to access this register depends on the size of the address bus During memory to memory transfers this register stores...

Page 21: ...s the channel s hardware requests Auto initialization is disabled upon a reset Table 13 Command Register Non 8237 Mode Table 14 Mode Register Non 8237 Mode Bit Description 0 0 Controller enable 1 Cont...

Page 22: ...0 0 0 1 Base and current Word Count reg Current Word Count reg 0 0 1 0 1 Base and current Address reg Current DMA address reg 0 0 1 1 Base and current Word Count reg Current Word Count reg 0 1 0 0 2...

Page 23: ...of the bits select which channel to be programmed Program the Mode and Channel control registers of all the channels Write into the Address registers and Word Count register Enable the controller The...

Page 24: ...PFUs2 Registers sysMEM EBRs I O fMAX MHz 8237 dma_mc_o4_2_001 lpc 1258 200 524 N A 59 58 Non 8237 dma_mc_o4_2_002 lpc 2661 499 1187 N A 125 66 1 Performance and utilization characteristics are genera...

Page 25: ...ng the usage of IPexpress can be found in the IPexpress and ispLEVER help system For more information on the ispLEVER design tools visit the Lattice web site at www latticesemi com software Mode Name...

Page 26: ...nd is included as a standard feature of the ispLEVER design tools Details regarding the usage of IPexpress can be found in the IPexpress and ispLEVER help system For more information on the ispLEVER d...

Page 27: ...cluded as a standard feature of the ispLEVER design tools Details regarding the usage of IPexpress can be found in the IPexpress and ispLEVER help system For more information on the ispLEVER design to...

Page 28: ...d is included as a standard feature of the ispLEVER design tools Details regarding the usage of IPexpress can be found in the IPexpress and ispLEVER help system For more information on the ispLEVER de...

Page 29: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Lattice DMA MC E2 N3 DMA MC O4 N2 DMA MC XM N3 DMA MC XP N2 DMA MC SC N3...

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