Kontron CP6500-V, User Manual

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Configuration CP6500-V
Page 4 - 14 © 2005 Kontron Modular Computers GmbH ID 28945, Rev. 01
P R E L I M I N A R Y
2894
5.01.UG.VC.050304/09095
4
4.5.5 Watchdog, CompactPCI Interrupt Configuration Register
The interrupt configuration register holds a series of bits defining the interrupt routing for the
watchdog, the power control derate signal and the CompactPCI enumeration signal. If the
watchdog timer fails, it can generate three independent hardware events: reset, NMI and IRQ5
interrupt.
The enumeration signal is generated by a hot swap compatible board after insertion and prior
to removal. The system uses this interrupt signal to force software to configure the new board.
The derate signal indicates that the power supply is beginning to derate its power output.
Table 4-19: Watchdog, CompactPCI Interrupt Configuration Register
REGISTER NAME Interrupt Configuration Register ACCESS
ADDRESS 0x284 R W
BIT POSITION
MSB
7 6 5 4 3 2 1 0
LSB
CONTENT WNMI CFNMI CFIRQ CEIRQ CDIRQ WRST WIRQ HSIRQ
DEFAULT 0 0 0 0 0 0 0 0
BIT NAME VAL DESCRIPTION
0 HSIRQ 0 Disable hot swap handle IRQ5
1 Enable hot swap handle IRQ5
1 WIRQ 0 Disable Watchdog IRQ5 routing
1 Enable Watchdog IRQ5 routing
2 WRST 0 Disable Watchdog hardware reset
1 Enable Watchdog hardware reset
3 CDIRQ 0 Disable CPCI derate signal to IRQ5 routing
1 Enable CPCI derate signal to IRQ5 routing
4 CEIRQ 0 Disable CPCI enum signal to IRQ5 routing
1 Enable CPCI enum signal to IRQ5 routing
5 CFIRQ 0 Disable CPCI fail signal to IRQ5 routing
1 Enable CPCI fail signal to IRQ5 routing
6 CFNMI 0 Disable CPCI fail signal to NMI routing
1 Enable CPCI fail signal to NMI routing
7 WNMI 0 Disable Watchdog NMI routing
1 Enable Watchdog NMI routing
Note ...
To enable the dual stage watchdog, the NMI and the reset bits must be set. At
the first stage the watchdog generates an NMI, and at the second stage the
system will be reset.