Kontron CP6500-V, User Manual

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CP6500-V Configuration
ID 28945, Rev. 01 © 2005 Kontron Modular Computers GmbH Page 4 - 11
P R E L I M I N A R Y
2894
5.01.UG.VC.050304/09095
4
4.5 Special Registers Description
The following registers are special registers which the CP6500-V uses to watch the onboard
hardware special features and the CompactPCI control signals.
Normally, only the system BIOS uses these registers, but they are documented here for
application use as required.
4.5.1 Watchdog
The CP6500-V has one watchdog timer. This timer is provided with a programmable timeout
ranging from 125 msec to 256 sec. Failure to strobe the watchdog timer within a set time period
results in a system reset, NMI or an interrupt. This can be configured via the 0x284 register.
To enable the watchdog, bit ”4” of the 0x282 register must be set. If the watchdog is enabled
via bit ”4”, this bit cannot be cleared later.
With a write access to the 0x280 register the watchdog is retriggered. Once the watchdog is
enabled, it must be continuously strobed within the terminal count period to avoid resetting the
system hardware.
The watchdog can be configured in several modes, one of which is the dual stage
configuration. If the NMI and the reset configuration bits are set (0x284 = 0x84), the watchdog
has two stages. The first stage timeout generates an NMI interrupt. If the NMI handler does not
reconfigure the watchdog, the watchdog switches to the second stage and generates a master
reset after the configured timeout elapses.
4.5.2 Watchdog Trigger
A write access triggers the watchdog.
The I/O location for the watchdog trigger is 0x280.
Note ...
Take care when modifying the contents of these registers as the system BIOS
may be relying on the state of the bits under its control.