COMe-bKL6 – User Guide Rev.1.2
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6.2.3.2.
Chipset > PCH-IO Configuration
Figure 9: PCH-IO Configuration Menu Initial Screen
The following table shows the PCH-IO sub-screens and functions, and describes the content. Default settings are in
bold and some functions include additional information.
Table 33: Chipset Set > PCH-IO Configuration Sub-screens and Functions
Function
Second level Sub-Screen / Description
PCI Express
Configuration>
PCI Express
Clock Gating>
PCI Express clock gating for each root port
[Enabled, Disabled]
Legacy IO Low
Latency>
Enables low latency of legacy I/O as some systems require lower I/O
latency irrespective of power. This is a tradeoff between power and I/O
latency.
[Enabled, Disabled]
DMI Link ASPM
Control>
Control of Active State Power Management on SA side of DMI link
[Enabled, Disabled]
PCIE Port
Assigned toLAN>
Read Only file
This port is always 5.
[5]
Port8xh Decode> PCI express port 8xh decode
[Enabled, Disabled]
PCI Express
Clock Gating>
PCI Express clock gating for each root port
[Enabled, Disabled]
