Keithley KPCI-3110, User Manual

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KPCI-3110 and KPCI-3116 User’s Manual Functional Description 2-19
Analog output conversion modes
KPCI-3110 and KPCI-3116 boards support the following conversion modes:
• Single value (polled) operations are the simplest to use but offer the least flexibility and
efficiency. Use software to specify the range, gain, and analog output channel (among other
parameters), and output the data from that channel. For a single value operation, you cannot
specify a clock source, trigger source, or buffer.
Single value operations stop automatically when finished; you cannot stop a single value
operation.
• Continuous analog output operations take full advantage of the capabilities of the
KPCI-3110 and KPCI-3116 boards. In this mode, you can specify an analog output channel-
gain list, clock source, trigger source, buffer, and buffer wrap mode. Two continuous analog
output operations are supported: continuously-paced and waveform generation mode. These
modes are described in the following subsections.
Using DriverLINX software, you can stop a scan when the hardware fills the host buffer you
specified or when your application issues a stop command.
Continuously-paced analog output
Use continuously-paced analog output mode if you want to accurately control the period
between conversions of individual analog output channels in the analog output channel list.
The host computer transfers digital values to write to the DACs from allocated circular buffers in
computer memory to the Output FIFO on the board. KPCI-3110 and KPCI-3116 boards have a 4
kSample Output FIFO. Use software to allocate the number of buffers and to specify the values.
When it detects a trigger, the board outputs the values in the Output FIFO to the DACs at the
same time. Even samples (0, 2, 4, and so on) are written to entry 0 in the channel list; odd sam-
ples (1, 3, 5, and so on) are written to entry 1 in the channel list. The operation repeats continu-
ously until either all the data is output from the buffers (if buffer wrap mode is none) or if you
stop the operation (if buffer wrap mode is multiple). Refer to
page 2-20 for more information on
buffers.
Ensure that the host computer transfers data to the Output FIFO fast enough so that the Output
FIFO does not empty completely; otherwise, an Output FIFO Underrun error results. Note that
the Output FIFO Counter increments each time the host loads a value into the Output FIFO and
decrements each time the DAC reads a value from the Output FIFO; the counter is reset to 0
when the Output FIFO is reset. To avoid the Output FIFO Underrun error in continuously-paced
mode, the host computer can read the Output FIFO Counter to determine how many samples
remain in the Output FIFO, and transfer more data before the Output FIFO empties.
The conversion rate is determined by the frequency of the D/A output clock. For KPCI-3110
boards, the maximum throughput rate in this mode is 500 (500 kSamples/s) in 100mV steps. For
KPCI-3116 boards, the maximum throughput rate in this mode is 200kHz (200 kSamples/s) in
100mV steps. Note that rate is system dependent. Refer to
page 2-17 for more information on
the D/A output clock.