Keithley KPCI-3110, User Manual

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KPCI-3110 and KPCI-3116 User’s Manual Functional Description 2-9
Specify the retrigger frequency as follows:
For example, if you are using 512 channels in the channel-gain list (CGL), scanning the channel-
gain list 256 times every trigger or retrigger, and using an A/D sample clock with a frequency of
1MHz, set the maximum retrigger frequency to 7.62Hz, since:
To select internally-retriggered scan mode, use software to specify the following parameters:
• The dataflow as continuous, continuous pre-trigger, or continuous about-trigger.
• Triggered scan mode usage as enabled.
• The retrigger mode as internal.
• The number of times to scan per trigger or retrigger (also called the multiscan count).
• The frequency of the retrigger clock.
The initial trigger source depends on the trigger acquisition mode selected. Refer to page 2-10
for more information on the supported trigger acquisition modes and trigger sources.
NOTE An A/D Trigger Out signal is provided for your use. This signal is high
when the A/D subsystem is waiting for a trigger and low when a trigger
occurs. In internally-retriggered scan mode, this signal stays low until
the desired number of samples have been acquired, then goes high until
the internal retrigger is generated.
Externally-retriggered scan mode (external clock: burst mode)
Use externally-retriggered scan mode if you want to accurately control the period between con-
versions of individual channels and retrigger the scan based on an external event. Like inter-
nally-retriggered scan mode, this mode allows you to acquire 262,144 samples per trigger (256
times per trigger x 1024-location channel-gain list).
NOTE Use externally-retriggered scan mode with continuous post-trigger
acquisitions only. Refer to
page 2-11 for more information on post-trig-
ger acquisitions.
When a KPCI-3110 or KPCI-3116 board detects an initial trigger (post-trigger source only), the
board scans the channel-gain list up to 256 times, then waits for an external retrigger to occur.
Specify any supported post-trigger source as the initial trigger. For the retrigger, specify either
an external digital (TTL) trigger or an external analog threshold trigger.
When the retrigger occurs, the board scans the channel-gain list the specified number of times,
then waits for another external retrigger to occur. The process repeats continuously until either
the allocated buffers are filled or you stop the operation. Refer to
page 2-15 for more informa-
tion on buffers.
Min. Retrigger Period
No. of CGL entries No. of CGLs per trigger
×
A/D sample clock frequency
---------------------------------------------------------------------------------------------------------------- 2
µ
s +
 
 
=
Max. Retrigger
1
Frequency Min. Retrigger Period
------------------------------------------------------------------------------- =
7.62Hz
1
512 256
× ( )
MHz
----------------------------- 2
µ
s +
 
 
-------------------------------------------------- =