Errata
Intel
®
Core™2 Extreme Quad-Core Processor QX6000
Δ
Sequence and
33
Intel
®
Core™2 Quad Processor Q6000
Δ
Sequence
Specification Update
AK33.
Unsynchronized Cross-Modifying Code Operations Can Cause
Unexpected Instruction Execution Results
Problem:
The act of one processor, or system bus master, writing data into a currently
executing code segment of a second processor with the intent of having the
second processor execute that data as code is called cross-modifying code
(XMC). XMC that does not force the second processor to execute a
synchronizing instruction, prior to execution of the new code, is called
unsynchronized XMC.
Software using unsynchronized XMC to modify the instruction byte stream of a
processor can see unexpected or unpredictable execution behavior from the processor
that is executing the modified code.
Implication:
In this case, the phrase "unexpected or unpredictable execution behavior"
encompasses the generation of most of the exceptions listed in the Intel
Architecture Software Developer's Manual Volume 3: System Programming
Guide, including a General Protection Fault (GPF) or other unexpected
behaviors. In the event that unpredictable execution causes a GPF the
application executing the unsynchronized XMC operation would be terminated
by the operating system.
Workaround:
To avoid this erratum, programmers should use the XMC synchronization
algorithm as detailed in the Intel Architecture Software Developer's Manual
Volume 3: System Programming Guide, Section: Handling Self- and Cross-
Modifying Code.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK34.
MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
Problem:
When an MCE occurs during execution of a RDMSR instruction for MSRs
Actual Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock
Count (IA32_MPERF), the current and subsequent RDMSR instructions for
these MSRs may contain incorrect data.
Implication:
After an MCE event, accesses to the IA32_APERF and IA32_MPERF MSRs may
return incorrect data. A subsequent reset will clear this condition.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK35.
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
Problem:
A partial memory state save of the 512-byte FXSAVE image or a partial
memory state restore of the FXRSTOR image may occur if a memory address
exceeds the 64KB limit while the processor is operating in 16-bit mode or if a
