Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor, Specification

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Errata
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Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ
Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence
Specification Update
•
FIST m32int
•
FISTP m16int
•
FISTP m32int
•
FISTP m64int
•
FISTTP m16int
• FISTTP m32int
• FISTTP m64int
Note that even if this combination of instructions is encountered, there is also a
dependency on the internal pipelining and execution state of both instructions in the
processor.
Implication:
Inexact-result exceptions are commonly masked or ignored by applications,
as it happens frequently, and produces a rounded result acceptable to most
applications. The PE bit of the FPU status word may not always be set upon
receiving an inexact-result exception. Thus, if these exceptions are
unmasked, a floating-point error exception handler may not recognize that a
precision exception occurred. Note that this is a "sticky" bit, i.e., once set by
an inexact-result condition, it remains set until cleared by software.
Workaround:
This condition can be avoided by inserting either three NOPs or three non-
floating-point non-Jcc instructions between the two floating-point
instructions.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK21. Global Pages in the Data Translation Look-Aside Buffer (DTLB) May
Not Be Flushed by RSM instruction before Restoring the Architectural
State from SMRAM
Problem:
The Resume from System Management Mode (RSM) instruction does not
flush global pages from the Data Translation Look-Aside Buffer (DTLB) prior
to reloading the saved architectural state.
Implication:
If SMM turns on paging with global paging enabled and then maps any of
linear addresses of SMRAM using global pages, RSM load may load data from
the wrong location.
Workaround:
Do not use global pages in system management mode.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK22. Sequential Code Fetch to Non-canonical Address May have Non-
deterministic Results
Problem:
If code sequentially executes off the end of the positive canonical address
space (falling through from address 00007fffffffffff to non- canonical address
0000800000000000), under some circumstances the code fetch will be
converted to a canonical fetch at address ffff800000000000.