Errata
34
Intel
®
Core™2 Extreme Quad-Core Processor QX6000
Δ
Sequence and Intel
®
Core™2 Quad Processor Q6000
Δ
Sequence
Specification Update
memory address exceeds the 4 GB limit while the processor is operating in
32-bit mode.
Implication:
FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as
expected but the memory state may be only partially saved or restored.
Workaround:
Software should avoid memory accesses that wrap around the respective 16-
bit and 32-bit mode memory limits.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK36.
Split Locked Stores May not Trigger the Monitoring Hardware
Problem:
Logical processors normally resume program execution following the MWAIT,
when another logical processor performs a write access to a WB cacheable
address within the address range used to perform the MONITOR operation.
Due to this erratum, a logical processor may not resume execution until the
next targeted interrupt event or O/S timer tick following a locked store that
spans across cache lines within the monitored address range.
Implication:
The logical processor that executed the MWAIT instruction may not resume
execution until the next targeted interrupt event or O/S timer tick in the case
where the monitored address is written by a locked store which is split across
cache lines.
Workaround:
Do not use locked stores that span cache lines in the monitored address
range.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK37.
REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode
when RCX >= 0X100000000
Problem:
REP CMPS (Compare String) and SCAS (Scan String) instructions in 64-bit
mode may terminate before the count in RCX reaches zero if the initial value
of RCX is greater than or equal to 0X100000000.
Implication:
Early termination of REP CMPS/SCAS operation may be observed and RFLAGS
may be incorrectly updated.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK38.
FXSAVE/FXRSTOR Instructions which Store to the End of the
Segment and Cause a Wrap to a Misaligned Base Address (Alignment
<= 0x10h) May Cause FPU Instruction or Operand Pointer Corruption
Problem:
If a FXSAVE/FXRSTOR instruction stores to the end of the segment causing a
wrap to a misaligned base address (alignment <= 0x10h), and one of the
following conditions is satisfied:
1)
32-bit addressing, obtained by using address-size override, when in 64-bit mode
