Errata
62
Intel
®
Core™2 Extreme Quad-Core Processor QX6000
Δ
Sequence and Intel
®
Core™2 Quad Processor Q6000
Δ
Sequence
Specification Update
Implication:
Software that uses aliasing between cacheable and WC memory types may
observe memory ordering errors within WC memory operations. Intel has not
observed this erratum with any commercially available software.
Workaround:
None identified. Intel does not support the use of cacheable and WC memory
type aliasing, and WC operations are defined as weakly ordered.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK118.
VM Exit due to Virtual APIC-Access May Clear RF
Problem:
RF (Resume Flag), bit 16 of the EFLAGS/RFLAGS register, is used to restart
instruction execution without getting an instruction breakpoint on the
instruction following a debug breakpoint exception. Due to this erratum, in a
system supporting Intel
®
Virtualization Technology, when a VM Exit occurs
due to Virtual APIC-Access (Advanced Programmable Interrupt Controller-
Access) the EFLAGS/RFLAGS saved in the VMCS (Virtual-Machine Control
Structure) may contain an RF value of 0.
Implication:
When this erratum occurs, following a VM Exit due to a Virtual APIC-access,
the processor may unintentionally break on the subsequent instruction after
VM entry.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK119.
RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
Problem:
RSM instruction execution, under certain conditions triggered by a complex
sequence of internal processor micro-architectural events, may lead to
processor hang, or unexpected instruction execution results.
Implication:
In the above sequence, the processor may live lock or hang, or RSM
instruction may restart the interrupted processor context through a
nondeterministic EIP offset in the code segment, resulting in unexpected
instruction execution, unexpected exceptions or system hang. Intel has not
observed this erratum with any commercially available software.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK120.
NMIs May Not Be Blocked by a VM-Entry Failure
Problem:
The
Intel
®
64 and IA-32 Architectures Software Developer’s Manual Volume
3B: System Programming Guide,
Part 2 specifies that, following a VM-entry
failure during or after loading guest state, “the state of blocking by NMI is
what it was before VM entry.” If non-maskable interrupts (NMIs) are blocked
and the “virtual NMIs” VM-execution control set to 1, this erratum may result
