Errata
42
Intel
®
Core™2 Extreme Quad-Core Processor QX6000
Δ
Sequence and Intel
®
Core™2 Quad Processor Q6000
Δ
Sequence
Specification Update
Workaround:
Software should avoid crossing page boundaries from WB or WC memory
type to UC, WP or WT memory type within a single REP MOVS or REP STOS
instruction that will execute with fast strings enabled.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK60.
MOV To/From Debug Registers Causes Debug Exception
Problem:
When in V86 mode, if a MOV instruction is executed to/from on debug
register, a general-protection exception (#GP) should be generated.
However, in the case when the general detect enable flag (GD) bit is set, the
observed behavior is that a debug exception (#DB) is generated instead.
Implication:
With debug-register protection enabled (i.e., the GD bit set), when
attempting to execute a MOV on debug registers in V86 mode, a debug
exception will be generated instead of the expected general-protection fault.
Workaround:
In general, operating systems do not set the GD bit when they are in V86
mode. The GD bit is generally set and used by debuggers. The debug
exception handler should check that the exception did not occur in V86 mode
before continuing. If the exception did occur in V86 mode, the exception may
be directed to the general-protection exception handler.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK61.
Unaligned Accesses to Paging Structures May Cause the Processor to
Hang
Problem:
When an unaligned access is performed on paging structure entries,
accessing a portion of two different entries simultaneously, the processor
may live lock.
Implication:
When this erratum occurs, the processor may live lock causing a system
hang.
Workaround:
Do not perform unaligned accesses on paging structure entries.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK62.
EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits
after a Translation Change
Problem:
This erratum is regarding the case where paging structures are modified to
change a linear address from writable to non-writable without software
performing an appropriate TLB invalidation. When a subsequent access to
that address by a specific instruction (ADD, AND, BTC, BTR, BTS, CMPXCHG,
DEC, INC, NEG, NOT, OR, ROL/ROR, SAL/SAR/SHL/SHR, SHLD, SHRD, SUB,
XOR, and XADD) causes a page fault, the value saved for EFLAGS may
incorrectly contain the arithmetic flag values that the EFLAGS register would
have held had the instruction completed without fault. This can occur even if
the fault causes a VM exit or if its delivery causes a nested fault.
