Errata
64
Intel
®
Core™2 Extreme Quad-Core Processor QX6000
Δ
Sequence and Intel
®
Core™2 Quad Processor Q6000
Δ
Sequence
Specification Update
information field. In addition, the interruptibility-state field may indicate
blocking by STI or by MOV SS if such blocking were in effect before execution
of the INTn instruction or before execution of the VM-entry instruction that
injected the software interrupt.
Implication:
In general, VMM software that follows the guidelines given in the section
“Handling VM Exits Due to Exceptions” of
Intel
®
64 and IA-32 Architectures
Software Developer’s Manual Volume 3B: System Programming Guide
should
not be affected. If the erratum improperly causes indication of blocking by
STI or by MOV SS, the ability of a VMM to inject an interrupt may be delayed
by one instruction.
Workaround:
VMM software should follow the guidelines given in the section “Handling VM
Exits Due to Exceptions” of
Intel
®
64 and IA-32 Architectures Software
Developer’s Manual Volume 3B: System Programming Guide
.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK124.
A VM Exit Occurring in IA-32e Mode May Not Produce a VMX Abort
When Expected
Problem:
If a VM exit occurs while the processor is in IA-32e mode and the “host
address-space size” VM-exit control is 0, a VMX abort should occur. Due to
this erratum, the expected VMX aborts may not occur and instead the VM Exit
will occur normally. The conditions required to observe this erratum are a VM
entry that returns from SMM with the “IA-32e guest” VM-entry control set to
1 in the SMM VMCS and the “host address-space size” VM-exit control cleared
to 0 in the executive VMCS.
Implication:
A VM Exit will occur when a VMX Abort was expected.
Workaround:
An SMM VMM should always set the “IA-32e guest” VM-entry control in the
SMM VMCS to be the value that was in the LMA bit (IA32_EFER.LMA.LMA[bit
10]) in the IA32_EFER MSR (C0000080H) at the time of the last SMM VM
exit. If this guideline is followed, that value will be 1 only if the “host
address-space size” VM-exit control is 1 in the executive VMCS.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK125.
A Page Fault May Not be Generated When the PS bit is set to “1” in a
PML4E or PDPTE
Problem:
On processors supporting Intel
®
64 architecture, the PS bit (Page Size, bit 7)
is reserved in PML4Es and PDPTEs. If the translation of the linear address of a
memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault
should occur. Due to this erratum, PS of such an entry is ignored and no
page fault will occur due to its being set.
Implication:
Software may not operate properly if it relies on the processor to deliver page
faults when reserved bits are set in paging-structure entries.
