Intel BX80562Q6600 - Core 2 Quad 2.4 GHz Processor Specification Download Page 3

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Preface

Intel

Core™2 Extreme Quad-Core Processor QX6000

Sequence and

Intel

Core™2 Quad Processor Q6000

Sequence

Specification Update

Contents

Preface ...............................................................................................................................6

Summary Tables of Changes ..................................................................................................8

Identification Information .................................................................................................... 18

Component Identification Information .................................................................................... 19

Errata ............................................................................................................................... 21

Specification Changes ......................................................................................................... 67

Specification Clarifications ................................................................................................... 68

Documentation Changes ...................................................................................................... 69

Summary of Contents for BX80562Q6600 - Core 2 Quad 2.4 GHz Processor

Page 1: ...g Intel 64 Architecture and Intel Virtualization Technology December 2010 Document Number 315593 027 Notice The Intel Core 2 Extreme quad core processor and Intel Core 2 quad processor may contain des...

Page 2: ...nd a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality The Intel Core 2 Extreme quad core processor and Intel Core 2 Quad pr...

Page 3: ...ntel Core 2 Quad Processor Q6000 Sequence Specification Update Contents Preface 6 Summary Tables of Changes 8 Identification Information 18 Component Identification Information 19 Errata 21 Specificat...

Page 4: ...QX6800 processor information Changed document title to Intel Core 2 Extreme Quad Core Processor QX6000 Sequence and Intel Core 2 Quad Processor Q6000 Sequence April 2007 Out of Cycle 008 Added Erratum...

Page 5: ...atum AK119 Nov 2007 019 Updated Erratum AK8 Added Erratum AK120 Dec 2007 020 Added Erratum AK121 Jan 2008 021 Updated Erratum AK51 Added Erratum AK122 Feb 13th 2008 022 Added Erratum AK123 AK124 May 2...

Page 6: ...tain information that has not been previously published Affected Documents Document Title Document Number Intel Core 2 Extreme Quad Core Processor QX6700 and Intel Core 2 Quad Processor Q6000 Sequence...

Page 7: ...esigned to be used with any given stepping must assume that all errata documented for that stepping are present on all devices Specification Changes are modifications to the current published specific...

Page 8: ...ng issues through documentation or Specification Changes as noted This table uses the following notations Codes Used in Summary Table Stepping X Erratum Specification Change or Clarification that appl...

Page 9: ...n processor Q Mobile Intel Pentium 4 processor supporting Hyper Threading technology on 90 nm process technology R Intel Pentium 4 processor on 90 nm process S 64 bit Intel Xeon processor with 800 MHz...

Page 10: ...Intel Core 2 Quad processor Q9000 series AW Intel Core 2 Duo processor E8000 series AX Quad Core Intel Xeon processor 5400 series AY Dual Core Intel Xeon processor 5200 series AZ Intel Core 2 Duo Pro...

Page 11: ...ter PMH_PAGE_WALK May be Incorrect AK14 X X No Fix LER MSRs May be Incorrectly Updated AK15 X X No Fix Performance Monitoring Events for Retired Instructions C0H May Not Be Accurate AK16 X X No Fix Pe...

Page 12: ...k Count IA32_APERF or Maximum Frequency Clock Count IA32_MPERF May Contain Incorrect Data after a Machine Check Exception MCE AK35 X X No Fix Incorrect Address Computed For Last Byte of FXSAVE FXRSTOR...

Page 13: ...ith Memory Types WB WT May Lead to Unpredictable Behavior AK56 X Fixed Update of Read Write R W or User Supervisor U S or Present P Bits without TLB Shootdown May Cause Unexpected Processor Behavior A...

Page 14: ...R6 May Not be Properly Cleared After Code Breakpoint AK77 X X No Fix BTM BTS Branch From Instruction Address May be Incorrect for Software Interrupts AK78 X X No Fix Last Branch Records LBR Updates Ma...

Page 15: ...ctly for PMULUDQ Instruction AK97 X X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI AK98 X Fixed Processor On Die Termination of BR1 and LOCK Signals are Incorrect AK99 X...

Page 16: ...WC Memory Types May Lead to Memory Ordering Violations AK118 X X No Fix VM Exit due to Virtual APIC Access May Clear RF AK119 X X No Fix RSM Instruction Execution under Certain Conditions May Cause P...

Page 17: ...ification Update Number SPECIFICATION CHANGES There are no Specification Changes in this Specification Update revision Number SPECIFICATION CLARIFICATIONS There are no Specification Clarifications in...

Page 18: ...Sequence Specification Update Identification Information Figure 1 Intel Core 2 Extreme quad core processor Package ATPO S N INTEL 05 QX6700 INTEL CORE 2 EXTREME SLxxx COO 2 66GHZ 8M 1066 05B FPO M e4...

Page 19: ...n the EAX register Refer to the Intel Processor Identification and the CPUID Instruction Application Note AP 485 and the Conroe and Woodcrest Processor Family BIOS Writer s Guide BWG for further infor...

Page 20: ...These parts have PROCHOT enabled 7 These parts have THERMTRIP enabled 8 These parts support Thermal Monitor 2 TM2 feature 9 These parts have PECI enabled 10 These parts have Enhanced Intel SpeedStep...

Page 21: ...pected interrupts that may occur The ISR associated with the spurious vector does not generate an EOI therefore the spurious vector should not be used when writing the LVT Status For the steppings aff...

Page 22: ...teppings affected see the Summary Tables of Changes AK5 DR3 Address Match on MOVD MOVQ MOVNTQ Memory Store Instruction May Incorrectly Increment Performance Monitoring Count for Saturating SIMD Instru...

Page 23: ...ant prefixes are placed before the instruction Workaround None identified Status For the steppings affected see the Summary Tables of Changes AK8 Pending x87 FPU Exceptions MF Following STI May Be Ser...

Page 24: ...d way For example if an instruction that masks the interrupt flag e g CLI is executed soon after an uncacheable write to the Task Priority Register TPR that lowers the APIC priority the interrupt mask...

Page 25: ...Changes AK14 LER MSRs May be Incorrectly Updated Problem The LER Last Exception Record MSRs MSR_LER_FROM_LIP 1DDH and MSR_LER_TO_LIP 1DEH may contain incorrect values after any of the following Either...

Page 26: ...or with mask 1 counts a value lower than expected The value is lower by exactly one multiple of the maximum possible ratio Workaround Multiply the performance monitor value by the maximum possible rat...

Page 27: ...gabyte Limit Check Problem Code Segment limit violation may occur on 4 Gigabyte limit check when the code stream wraps around in a way that one instruction ends at the last byte of the segment and the...

Page 28: ...ree NOPs or three non floating point non Jcc instructions between the two floating point instructions Status For the steppings affected see the Summary Tables of Changes AK21 Global Pages in the Data...

Page 29: ...e that all VMCS reserved bits are set to values consistent with VMX Capability MSRs Status For the steppings affected see the Summary Tables of Changes AK24 The PECI Controller Resets to the Idle Stat...

Page 30: ...n of the instruction will have executed before the exception handler is entered If an instruction that performs a memory load causes a code segment limit violation If a waiting X87 floating point FP i...

Page 31: ...s diagnostic software that relies on a valid EIP Workaround None identified Status For the steppings affected see the Summary Tables of Changes AK29 GP Fault is Not Generated on Writing IA32_MISC_ENAB...

Page 32: ...ctions x87 exceptions on FST and FBSTP instructions Breakpoint matches on loads stores and I O instructions Stores which update the A and D bits Stores that split across a cache line VMX transitions A...

Page 33: ...pplication executing the unsynchronized XMC operation would be terminated by the operating system Workaround To avoid this erratum programmers should use the XMC synchronization algorithm as detailed...

Page 34: ...ay not resume execution until the next targeted interrupt event or O S timer tick in the case where the monitored address is written by a locked store which is split across cache lines Workaround Do n...

Page 35: ...the request is sent to the L2 cache If this request hits a modified line in the L1 data cache of Core 2 certain internal conditions may cause incorrect data to be returned to the Core 1 Implication T...

Page 36: ...d None identified Status For the steppings affected see the Summary Tables of Changes AK43 Concurrent Multi processor Writes to Non dirty Page May Result in Unpredictable Behavior Problem When a logic...

Page 37: ...package that have not observed the error condition may be disabled and may not respond to INIT SMI NMI SIPI or other events Workaround When this erratum occurs RESET must be asserted to restore multi...

Page 38: ...ocessor will no longer be in VM86 mode Normally operating systems should prevent interrupt task switches from faulting thus the scenario should not occur under normal circumstances Workaround None Ide...

Page 39: ...Incorrect after a Task Switch Problem A Task State Segment TSS task switch may incorrectly set the LBR_FROM value to the LBR_TO value Implication The LBR_FROM will have the incorrect address of the B...

Page 40: ...ach with different memory type Memory type aliasing with the memory types WB and WT may cause the processor to perform incorrect operations leading to unpredictable behavior Implication Software that...

Page 41: ...LODSB or SCASB may terminate without completing the last iteration Intel has not observed this erratum with any commercially available software Workaround Do not use repeated string operations with R...

Page 42: ...e continuing If the exception did occur in V86 mode the exception may be directed to the general protection exception handler Status For the steppings affected see the Summary Tables of Changes AK61 U...

Page 43: ...r canonical boundary 0x00007FFFFFFFFFFF in 64 bit mode the LBR return registers will save a wrong return address with bits 63 to 48 incorrectly sign extended to all 1s Subsequent BTS and BTM operation...

Page 44: ...ummary Tables of Changes AK67 IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Problem In IA 32e mode it is possible to get an Alignment Check Exception AC on the IRET i...

Page 45: ...escribed conditions Workaround None identified Status For the steppings affected see the Summary Tables of Changes AK70 PEBS Does Not Always Differentiate Between CPL Qualified Events Problem Performa...

Page 46: ...Single Step bit 14 flag may be incorrectly set when the TF Trap Flag bit 8 of the EFLAGS Register is set and a DB Debug Exception occurs due to one of the following DR7 GD General Detect bit 13 being...

Page 47: ...guest Workaround A Virtual Machine Monitor must manually disregard the BS bit in the Guest State Area in case of a VM exit due to a TPR value below the TPR threshold Status For the steppings affected...

Page 48: ...or may live lock and or result in a system hang Workaround It is possible for BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary Tables of Changes AK80 Per...

Page 49: ...cted see the Summary Tables of Changes AK83 CPUID Reports Architectural Performance Monitoring Version 2 is Supported When Only Version 1 Capabilities are Available Problem CPUID leaf 0Ah reports the...

Page 50: ...structions Due to this erratum the processor may inaccurately also count certain other types of instructions resulting in higher than expected values Implication Performance Monitoring counter SIMD_IN...

Page 51: ...ook aside Buffer TLB entries for large pages 2M 4M when both of the following conditions exist Address range of the page being invalidated spans several Memory Type Range Registers MTRRs with differen...

Page 52: ...ructions May Lead to Unexpected Behavior Problem Invalid instructions due to undefined opcodes or instructions exceeding the maximum instruction length due to redundant prefixes placed before the inst...

Page 53: ...io The stack size was changed due to a SYSEXIT or SYSRET PVI Protected Mode Virtual Interrupts mode was enabled CR4 PVI 1 Both the VIF Virtual Interrupt Flag and VIP Virtual Interrupt Pending flags of...

Page 54: ...BR1 and LOCK signals are incorrect BR 1 has its On Die Termination continuously enabled and LOCK has its On Die Termination continuously disabled Implication BR1 has its On Die Termination continuous...

Page 55: ...tatus For the steppings affected see the Summary Tables of Changes AK101 Performance Monitoring Event CPU_CLK_UNHALTED REF May Not Count Clock Cycles According to the Processors Operating Frequency Pr...

Page 56: ...rmance monitoring event MISALIGN_MEM_REF 05H is used to count the number of memory accesses that cross an 8 byte boundary and are blocked until retirement Due to this erratum the performance monitorin...

Page 57: ...ion Fault due to a WRMSR to one of the IA32_MTRR_PHYSMASKn MSRs with reserved bits set Implication When this erratum occurs a memory access may get an incorrect memory type leading to unexpected syste...

Page 58: ...h an overlap Under normal circumstances for correctly written software such an overlap is not expected to exist Intel has not observed this erratum with any commercially available software Workaround...

Page 59: ...around The VMM should emulate any event delivery that causes an APIC access VM exit in the same way regardless of the offset saved in the exit qualification Status For the steppings affected see the S...

Page 60: ...e non cacheable address is fetched in the IFU the processor may invalidate the non cacheable address from the fetch unit Any micro architectural event that causes instruction restart will be expecting...

Page 61: ...SS of the interruptibility state field of the guest state area of the VMCS bit 0 blocking by STI and bit 1 blocking by MOV POP SS should be left unmodified Implication Since the STI MOV SS and POP SS...

Page 62: ...ly break on the subsequent instruction after VM entry Workaround None identified Status For the steppings affected see the Summary Tables of Changes AK119 RSM Instruction Execution under Certain Condi...

Page 63: ...ault handler the processor may hang or may handle the benign exception Intel has not observed this erratum with any commercially available software Workaround None identified Status For the steppings...

Page 64: ...VM exit control is 0 a VMX abort should occur Due to this erratum the expected VMX aborts may not occur and instead the VM Exit will occur normally The conditions required to observe this erratum are...

Page 65: ...t to 1 a VM exit with exit reason NMI window should occur before execution of any instruction if there is no virtual NMI blocking no blocking of events by MOV SS and no blocking of events by STI If VM...

Page 66: ...n to ensure that no 80 bit FP accesses are wrapped around a 4 Gbyte boundary Status For the steppings affected see the Summary Tables of Changes AK129 A 64 bit Register IP relative Instruction May Ret...

Page 67: ...documents Intel Core 2 Extreme Quad Core Processor QX6700 and Intel Core 2 Quad Processor Q6000 Sequence Datasheet Intel Core 2 Extreme Quad Core Processor QX6800 Datasheet Intel 64 and IA 32 Architec...

Page 68: ...lowing documents Intel Core 2 Extreme Quad Core Processor QX6700 and Intel Core 2 Quad Processor Q6000 Sequence Datasheet Intel Core 2 Extreme Quad Core Processor QX6800 Datasheet Intel 64 and IA 32 A...

Page 69: ...eme Quad Core Processor QX6800 Datasheet All Documentation Changes will be incorporated into a future version of the appropriate Intel Core 2 Extreme Quad Core Processor and Intel Core 2 Quad processo...

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