Errata
48
Intel
®
Core™2 Extreme Quad-Core Processor QX6000
Δ
Sequence and Intel
®
Core™2 Quad Processor Q6000
Δ
Sequence
Specification Update
AK78.
Last Branch Records (LBR) Updates May be Incorrect After a Task
Switch
Problem:
A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM
value to the LBR_TO value.
Implication:
The LBR_FROM will have the incorrect address of the Branch Instruction.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK79.
REP Store Instructions in a Specific Situation may cause the
Processor to Hang
Problem:
During a series of REP (repeat) store instructions a store may try to dispatch
to memory prior to the actual completion of the instruction. This behavior
depends on the execution order of the instructions, the timing of a
speculative jump and the timing of an uncacheable memory store. All types
of REP store instructions are affected by this erratum.
Implication:
When this erratum occurs, the processor may live lock and/or result in a
system hang.
Workaround:
It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK80.
Performance Monitoring Events for L1 and L2 Miss May Not be
Accurate
Problem:
Performance monitoring events 0CBh with an event mask value of 02h or 08h
(MEM_LOAD_RETIRED.L1_LINE_MISS or
MEM_LOAD_RETIRED.L2_LINE_MISS) may under count the cache miss
events.
Implication:
Performance monitoring events 0CBh with an event mask value of 02h or 08h
may show a count which is lower than expected; the amount by which the
count is lower is dependent on other conditions occurring on the same load
that missed the cache.
Workaround:
None Identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK81.
Store to WT Memory Data May be Seen in Wrong Order by Two
Subsequent Loads
Problem:
When data of Store to WT memory is used by two subsequent loads of one
thread and another thread performs cacheable write to the same address the
first load may get the data from external memory or L2 written by another
core, while the second load will get the data straight from the WT Store.
