Intel 440GX, Design Manual

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Motherboard Layout and Routing Guidelines
2-14 Intel
®
440GX AGPset Design Guide
The methodology that Intel recommends is known as “Sensitivity Analysis”. In sensitivity analysis,
interconnect parameters are varied to understand how they affect system timing and signal
integrity. Sensitivity analysis can be further broken into two types of analysis, parametric sweeps
and Monte Carlo analysis, which are described below.
2.4 Placement & Layout
Once the pre-layout simulation is completed, route the board using the solution space resulting
from the sensitivity analysis.
2.5 Post-Layout Simulation
Following layout, extract the traces and run simulations to verify that the layout meets timing and
noise requirements. A small amount of trace “tuning” may be required, but experience at Intel has
shown that sensitivity analysis dramatically reduces the amount of tuning required.
The post layout simulations should take into account the expected variation for all interconnect
parameters. For timing simulations, use a V
REF
of 2/3 VTT ± 2% for both the Intel
®
Pentium
®
II
processor and Intel
®
440GX AGPset components. Flight times measured from the Pentium II
processor edge fingers to other system components use the standard flight time method.
Figure 2-13. Pre-layout simulation process
1
1 . 7 5
2 . 5
3 . 2 5
4
4 . 7 5
5 . 5
6 . 2 5
7
7 . 7 5
8 . 5
9 . 2 5
1 0
1 0 . 7 5
1 1 . 5
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4
4.25
4.5
4.75
5
5.25
5.5
5.75
6
-101
L1
PCard#1 to 82440FX Separation Distance (in)
L 2
P C a r d # 2 t o 8 2 4 4 0 F X S e p a r a t io n D i s t a n c e ( in )
D U A L K L A M A T H P R O C E S S O R C A R D S O L U T IO N S P A C E
R t = 5 6
Ω
+ / - 5 %
S o l u t io n s p a c e
M A X F l i g h t T i m e
L P C = 2 . 5 1 in ch e s
L F X = 1 .5 i n c h e s
L R T = 1 . 5 i n ch e s
M IN F l ig h t T i m e
L P C = 0 . 4 4 in ch e s
L F X = 0 .0 i n c h e s
L R T = 1 . 5 i n ch e s
V i ll a t io n s c a u s e d b y
m a x i m u m f li g h t t im e
V i ll a t io n s c a u s e d b y
m in im u m f lig h t t i m e
1
1.75 2.5
3.25
4
4.75 5.5
6.25
7
7.75 8.5
9.25
10
10.75 11.5
1
1. 75
2. 5
3. 25
4
4. 75
5. 5
0
0. 2
0. 4
0. 6
0. 8
1
1. 2
L 1
PC a rd #1 t o 82 44 0F X Se pa rat i on Di st an c e ( i n)
L 2
PC a rd #2 t o 82 44 0F X
Se p ar ati o n D is t an ce (i n )
D U A L K L A M A T H F L I G H T T I ME
M A X F T
LP C = 2. 51 inch es
LF X = 1 .5 inche s
LR T = 1.5 inc hes
R t = 53 .5 ohm s
M IN F T
LP C = 0. 44 inch es
LF X = 0 .0 inche s
LR T = 1.5 inc hes
R t = 53 .5 ohm s
8 24 40F X to K LA MA TH MIN FT RIS IN G (fast silic on - fas t boa rd)
1
1.75
2.5
3.25
4
4.75 5.5
6.25
7
7.75 8.5
9.25
10
10.75
11.5
1
1.7 5
2.5
3.2 5
4
4.7 5
5.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
L 1
PC ard #1 t o 8 244 0FX Se par atio n D ist a nce (i n )
L 2
PC ard #2 t o 8 244 0FX
Se pa rat io n Di sta nce ( in )
D U AL K L A MA TH FL I G HT T IM E
MA X F T
LP C = 2 .51 in ches
LF X = 1.5 inc hes
LR T = 1.5 inches
R t = 5 8.5 ohm s
MI N F T
LP C = 0 .44 in ches
LF X = 0.0 inc hes
LR T = 1.5 inches
R t = 5 8.5 ohm s
82 44 0FX to KLA MA TH
MA X FT RIS ING (s low silicon - slow board)
D U A L K L A M A T H P R O C E S S O R C A R D S O L U T IO N S P A C E
M o n t e C a rl o
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2
P C a r d t o 82 44 0 F X S e p ar at i o n D i s t a n c e (i n )
PCard to 82440FX Separation Distance (in)
Pa s s
Pa s s
F a il
F a il
Sensitivity Analyses
= KLAMATH1 X3
= KLAMATH1PIN X3 = KLAMATH2 X3
= KLAMATH2PIN X3
= 82440FXPIN 33
= ALL OTHERS = ALL OTHERS
0.25v
0.75v
1.25v
1.75v
0.00ns 20.00ns 40.00ns
X = 0.00ns y = +0.000v xdelta = 0.000ns
NET: SLOWDPNM_LS_12_6, DRIVER: KLAMATH1 TRACKING: KLAMATH1 X3 = KLAMATH1 X3
= KLAMATH1PIN X3
= KLAMATH2 X3
= KLAMATH2PIN X3
= 82440FXPIN 33 = ALL OTHERS = ALL OTHERS
0.25v
0.75v
1.25v
1.75v
0.00ns 20.00ns 40.00ns
X = 0.00ns y = +0.000v xdelta = 0.000ns
NET: SLOWDPNM_LS_12_6, DRIVER: KLAMATH2 TRACKING: KLAMATH1 X3 = KLAMATH1 X3
= KLAMATH1PIN X3 = KLAMATH2 X3
= KLAMATH2PIN X3
= 82440FXPIN 33
= ALL OTHERS = ALL OTHERS
0.25v
0.75v
1.25v
1.75v
0.00ns 20.00ns 40.00ns
X = 0.00ns y = +0.000v xdelta = 0.000ns
NET: SLOWDPNM_LS_12_6, DRIVER: KLAMATH1 TRACKING: KLAMATH1 X3 = KLAMATH1 X3
= KLAMATH1PIN X3
= KLAMATH2 X3
= KLAMATH2PIN X3
= 82440FXPIN 33 = ALL OTHERS = ALL OTHERS
0.25v
0.75v
1.25v
1.75v
0.00ns 20.00ns 40.00ns
X = 0.00ns y = +0.000v xdelta = 0.000ns
NET: SLOWDPNM_LS_12_6, DRIVER: KLAMATH2 TRACKING: KLAMATH1 X3
Interconnect Simulations (Transmission-Line)
Performance as function of Length
(flight time, signal quality, etc.)
Monte Carlo
(pass/fail as function of length)
Solution Space