Intel 440GX, Design Manual

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Intel
®
440GX AGPset Design Guide 4-6
Debug Recommendations
•
The Global Descriptor Table (GDT) must be aligned. The GDT must be located on a DWord
boundary, or else setting the PE bit and branching will cause a SHUTDOWN transaction.
•
The ITP “pins” command may be used to check reset configuration pin states. Be aware,
however, that observing pin state during reset will not reveal anything about the stability or
timing of the configuration signals around the reset edge.
•
You can expect the following processor system bus activity after reset: BNR# stops toggling
approximately 2.8 million BCLKs after the deassertion of RESET#, if BIST is not configured
to run. If BIST is configured to run, BNR# will continue to toggle until BIST completion.
After BNR# stops toggling, the PICD[1:0]# signals begin the MP initialization to determine
the bootstrap processor. In a single processor boot, two 21-cycle short messages are
transmitted on the APIC. (Refer to the Intel
®
Pentium
®
Pro Family Developer’s Manual, Vol.
III). The following fields are expected and all others are “don’t care.” Note that PICD[1:0]#
are active low so the pin electrical levels will be the complement of the numbers presented
here.
Interrupt Vector = 0x4N for the first cycle and 0x1N for the second cycle.
Where “N” is the processor number
DM = 0, D3-D0 = 1111 (all including self shorthand)
Trigger Mode = 1 (edge)
Level = 0 (deasserted)
Delivery Mode = 000 (fixed)