Intel 440GX, Design Manual

Page: 34 / 118

Motherboard Layout and Routing Guidelines
2-10 Intel
®
440GX AGPset Design Guide
2.3.6 Additional Guidelines
2.3.6.1 Minimizing Crosstalk
The following general rules will minimize the impact of crosstalk in the high speed GTL+ bus
design:
•
Maximize the space between traces. Maintain a minimum of 0.010” between traces wherever
possible. It may be necessary to use tighter spacings when routing between component pins.
•
Avoid parallelism between signals on adjacent layers.
•
Since GTL+ is a slow signal swing technology, it is important to isolate GTL+ signals from
other signals by at least 0.025”. This will avoid coupling from signals that have larger voltage
swings, such as 5V PCI.
•
Select a board stack-up that minimizes the coupling between adjacent signals.
•
Route GTL+ address, data and control signals in separate groups to minimize crosstalk
between groups. The Pentium II processor uses a split transaction bus. In a given clock cycle,
the address lines and corresponding control lines could be driven by a different agent than the
data lines and their corresponding control lines.
2.3.6.2 Practical Considerations
•
Distribute VTT with a wide trace. A 0.050” minimum trace is recommended to minimize DC
losses. Route the VTT trace to all components on the system bus. Be sure to include
decoupling capacitors. Guidelines for VTT distribution and decoupling are contained in Intel
®
Pentium
®
II Processor Power Distribution Guidelines.
•
Place resistor divider pairs for V
REF
generation at the Intel
®
440GX AGPset component. No
V
REF
generation is needed at the processor(s). V
REF
is generated locally on the processor. Be
sure to include decoupling capacitors. Guidelines for V
REF
distribution and decoupling are
contained in P Intel
®
Pentium
®
II Processor Power Distribution Guidelines.
•
There are six GTL+ signals that can be driven by more than one agent simultaneously. These
signals may require extra attention during the layout and validation portions of the design.
When a signal is asserted (driven low) by two agents on the same clock edge, the two falling
wave fronts will meet at some point on the bus. This can create a large undershoot, followed by
ringback which may violate the ringback specifications. This “wired-OR” situation should be
simulated for the following signals: AERR#, BERR#, BINIT#, BNR#, HIT#, and HITM#.
•
Lossless simulations can overstate the amount of ringing on GTL+ signals. Lossy simulations
may help to make your results less pessimistic if ringing is a problem. Intel has found the
resistivity of copper in printed circuit board signal layers higher than the value of
0.662
Ω
-mil
2
/in that has been published for annealed copper. Intel recommends using a value
of 1.0
Ω
-mil
2
/in for lossy simulations.
•
Higher R
TT
values tend to increase the amount of ringback on the rising edge, while smaller
values tend to increase the amount of ringback on the falling edge. It is not necessary to budget
for R
TT
variation if your simulations comprehend the expected manufacturing variation.
•
I/O Buffer models for the fast corner correspond to the minimum T
co
. Slow corner buffers will
be at least 500 ps slower. Therefore, it is only necessary to ensure that the minimum flight time
is met when the network is driven by fast buffer models.
•
I/O Buffer models for the slow corner correspond to the maximum T
co
. Fast corner buffers will
be at least 500 ps faster. It is only necessary to ensure that the maximum flight time is met
when the network is driven by slow buffer models, as long as no ringback problems exist.