Intel 440GX, Design Manual

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Intel
®
440GX AGPset Design Guide 1-5
Introduction
Figure 1-1 shows a block diagram of a typical platform based on the Intel
®
440GX AGPset. The
82443GX system bus interface supports up to two Intel
®
Pentium
®
II processors at the maximum
bus frequency of 100 MHz. The physical interface design is based on the GTL+ specification and is
compatible with the Intel
®
440GX AGPset solution. The 82443GX provides an optimized 72-bit
DRAM interface (64-bit Data plus ECC). This interface supports 3.3V DRAM technologies.
The 82443GX is designed to support the PIIX4E I/O bridge. The PIIX4E is a highly integrated
multifunctional component that supports the following functions and capabilities:
•
PCI Rev 2.1 compliant PCI-to-ISA Bridge with support for 33 MHz PCI operations
•
ACPI Desktop Power Management Support
•
Enhanced DMA controller and standard interrupt controller and timer functions
•
Integrated IDE controller with Ultra DMA/33 support
•
USB host interface with support for 2 USB ports
•
System Management Bus (SMB) with support for DIMM Serial Presence Detect
•
Support for an external I/O APIC component
1.3.2.1 System Bus Interface
The Intel
®
Pentium
®
II processor supports a second level cache size of 512 KB with ECC. All
cache control logic is provided on the processor. The 82443GX supports a maximum of 32 bit
address or 4 GB memory address space from the processor perspective. The 82443GX provides bus
control signals and address paths for transfers between the processors bus, PCI bus, Accelerated
Graphics Port and main memory. The 82443GX supports a 4-deep in-order queue (i.e., it provides
support for pipelining of up to 4 outstanding transaction requests on the system bus).
For system bus-to-PCI transfers, the addresses are either translated or directly forwarded on the
PCI bus, depending on the PCI address space being accessed. If the access is to a PCI configuration
space, the processor I/O cycle is mapped to a PCI configuration space cycle. If the access is to a
PCI I/O or memory space, the processor address is passed without modification to the PCI bus.
Certain memory address range (later referred in a document as a Graphics Aperture) are dedicated
for a graphics memory address space. If this space or portion of it is mapped to main DRAM, then
the address will be translated via the AGP address remapping mechanism and the request
forwarded to the DRAM subsystem. A portion of the graphics aperture can be mapped on AGP and
corresponding system bus cycles that hit that range are forwarded to AGP without any translation.
Other system bus cycles forwarded to AGP are defined by the AGP address map.
1.3.2.2 DRAM Interface
The 82443GX integrates a main memory controller that supports a 64/72-bit DRAM interface
which operates at 100 MHz. The integrated DRAM controller features: supports up to 4 double-
sided DIMMs, 8M to 256M using 16Mbit technology, 1 GB using 64Mbit technology, and 2 GB
using 128M or 256M technology, two copies of MAxx are provided for optimized timing, and ECC
with hardware scrubbing.
1.3.2.3 Accelerated Graphics Port Interface
The 82443GX supports an AGP interface. The AGP interface can reach a maximum theoretical
~532 Mbytes/sec transfer rate.