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Intel

®

440GX AGPset Design Guide

3-17

Design Checklist

IOCHCK#

Connected to ISA slots. 4.7K ohm pull-up to VCC.

IOCHRDY

Connected to ISA slots and Ultra I/O. 1K ohm pull-up to VCC.

IOCS16#

Connected to ISA slots. 1K ohm pull-up to VCC.

IOR#

Connected to ISA slots, Ultra I/O, LM79. 8.2K ohm pull-up to VCC.

IOW#

Connected to ISA slots, Ultra I/O, LM79. 8.2K ohm pull-up to VCC.

IRDY#

2.7K ohm pull-up to 5V or 10K ohm pull-up to 3V. Connect between 82443GX,
PCI slots, and PIIX4E.

IRQ0 / GPO14

UP: No connect. DP: Connected to INTIN2 of IOAPIC.

IRQ8#

8.2K ohm pull-up to 3VSB. DP: Connected to IOAPIC through tri-state buffer.

IRQ[1,3:7]

8.2K ohm pull-up to VCC. Connected to ISA slots and Ultra I/O.

DP: Connected to IOAPIC.

IRQ[15:14]

Connected to ISA slots, Ultra I/O, IDE. 8.2K ohm pull-up to VCC.

DP: Connected to IOAPIC.

IRQ[9:12]

Connected to ISA slots, Ultra I/O. 8.2K ohm pull-up to VCC.

DP: Connected to IOAPIC.

KBCCS# / GPO26

No Connect.

LA[17:23]

Connected to ISA slots. 8.2K ohm pull-up to VCC.

LID / GPI10

8.2K ohm pull-down if LID is not used. Connect to wake on LAN Header if used.

MCCS#

No connect.

MEMCS16#

Connected to ISA slots. 1K ohm pull-up to VCC.

MEMR#,

MEMW#

Connected to ISA slots and Flash. 8.2K ohm pull-up to VCC.

DP: Connected to IOAPIC.

NMI

Part of CPU/bus frequency circuit. 2.7K ohm pull-up to 3V.

OCx

Driven by USB overcurrent detection voltage divider.

OSC

Connect to CK100.

PAR

Connect to PCI slots and 82443GX.

PCICLK

Connect to CK100.

PCIRST#

Connect to AGP, PCI, and 82443GX.

PCI_STP# / GPO18

No connect, or connected to CK100 with 10K ohm pull-up to 3VSB.

PCS1#

Connected to IDE connector through 33 ohm series resistor.

PCS3#

Connected to IDE connector through 33 ohm series resistor.

PDA[2:0]

Connected to IDE connector through 33 ohm series resistors.

PDD[15:0]

Connected to IDE connector through 33 ohm series resistors. It is
recommended that PDD[7] have a 10K ohm pull-down resistor.

PDDACK#

Connected to IDE connector through 33 ohm series resistor.

PDIOR#

Connected to IDE connector through 33 ohm series resistor.

PDIOW#

Connected to IDE connector through 33 ohm series resistor.

PDREQ

Connected to IDE through 33 ohm series resistor. 5.6K ohm pull-down on the
PIIX4E side of the series resistor.

PGCS#0

No connect.

PGCS#1

8.2K ohm pull-up to VCC3. Connected to LM79.

Table 3-7. PIIX4E Connectivity (Sheet 2 of 4)

Signal Names

Connection

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Summary of Contents for 440GX

Page 1: ...Intel 440GX AGPset Design Guide March 1999 Order Number 290651 001...

Page 2: ...any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order The Intel 440GX AGPset may contain design d...

Page 3: ...idelines 2 1 2 1 BGA Quadrant Assignment 2 1 2 2 Board Description 2 3 2 3 Routing Guidelines 2 5 2 3 1 GTL Description 2 6 2 3 2 GTL Layout Recommendations 2 6 2 3 3 Single Processor Design 2 6 2 3 3...

Page 4: ...outing Spacing 2 32 2 9 6 2 System Bus Clock Layout 2 32 2 9 6 3 PCI Clock Layout 2 33 2 9 6 4 SDRAM Clock Layout 2 33 2 9 6 5 AGP Clock Layout 2 34 3 Design Checklist 3 1 3 1 Overview 3 1 3 2 Pull up...

Page 5: ...erature Sensor 3 33 3 18 2 LM79 Microprocessor System Hardware Monitor 3 33 3 18 3 82558B LOM Checklist 3 34 3 18 4 Wake On LAN WOL Header 3 35 3 19 Software BIOS 3 35 3 19 1 USB and Multi processor B...

Page 6: ...1 5 1 Processors 5 1 5 1 1 Voltage Regulator Modules 5 2 5 1 2 Voltage Regulator Control Silicon 5 2 5 2 Intel 440GX AGPset 5 3 5 2 1 Clock Drivers 5 3 5 2 2 Power Management Components 5 3 5 2 3 FET...

Page 7: ...Layout Guidelines 2 19 2 15 On board AGP Compliant Device Layout Guidelines 2 21 2 16 FET Switch Example 2 22 2 17 Registered SDRAM DIMM Example 2 23 2 18 Matching the Reference Planes and Adding Deco...

Page 8: ...2 16 Control Signal Line Length Recommendations 2 21 2 17 MDx lines Reference Planes Routing 2 23 2 18 FET Switch DQ Route Example 2 25 2 19 Motherboard Model SRAS_B 4 DIMMs 2 28 2 20 Motherboard Mod...

Page 9: ...Intel 440GX AGPset Design Guide ix Revision History Date Revision Description 3 99 001 Initial Release...

Page 10: ...x Intel 440GX AGPset Design Guide...

Page 11: ...1 Introduction...

Page 12: ......

Page 13: ...anageability of desktop mobile and server systems This chapter also provides design recommendations which Intel feels will provide flexibility to cover a broader range of products within a market segm...

Page 14: ...oper s Guide order number 243006 AP 485 CPUID Application Note WWW order number 41618 AP 585 Layout Application Note WWW order number 243330 AP 586 Thermal Application Note WWW order number 243331 AP...

Page 15: ...grated IDE Controller with Ultra DMA 33 support PIO Mode 4 transfers PCI IDE Bus Master support Integrated Universal Serial Bus USB Controller with 2 USB ports Integrated System Power Management Suppo...

Page 16: ...ngle and dual Intel Pentium II processor configurations 64 bit GTL based system data bus Interface 32 bit system address bus support 64 72 bit main memory interface with optimized support for SDRAM 32...

Page 17: ...rated Graphics Port and main memory The 82443GX supports a 4 deep in order queue i e it provides support for pipelining of up to 4 outstanding transaction requests on the system bus For system bus to...

Page 18: ...upts Chip select decoding is provided for BIOS Real Time Clock Keyboard Controller second external Microcontroller as well as 2 Programmable Chip Selects The PIIX4E provides full Plug and Play compati...

Page 19: ...and component instrumentation Information regarding this product can be found at http developer intel com ial WfM tools ldcm index htm The WfM Baseline Instrumentation specification identifies specifi...

Page 20: ...l Off Soft off is usually provided by a user accessible switch that will send a soft off request to the system The PIIX4 provides the power button input for this purpose and implementation details are...

Page 21: ...ing an open drain output driver with pull ups to Vcc2 5 3 Please prepare for additional thermal margin for increases of 1 5W for higher performance or otherwise enhanced processor 4 Motherboard design...

Page 22: ...Introduction 1 10 Intel 440GX AGPset Design Guide...

Page 23: ...2 Motherboard Design...

Page 24: ......

Page 25: ...motherboard to be routed in 4 layers Figure 2 1 shows the 4 signal quadrants of the 82443GX The component placement on the motherboard should be done with this general flow in mind This simplifies rou...

Page 26: ...actor design the AGP compliant graphics device can be either on the motherboard device down option or on an AGP connector up option 4 The trace length limitation between critical connections will be a...

Page 27: ...between the number of DIMM sockets and other motherboard peripherals need to be evaluated for each design 2 2 Board Description For a single processor Intel 440GX AGPset motherboard design a 4 layer...

Page 28: ...d in a Intel 440GX AGPset design If a 6 layer stack up is used then it is recommended to route most of the GTL bus signals on the inner layers The primary and secondary signal layer can be used for GT...

Page 29: ...or a short distance on a power plane then it should be routed on a VCC plane not the ground plane Keep vias for decoupling capacitors as close to the capacitor pads as possible 2 3 Routing Guidelines...

Page 30: ...L layout Guidelines for the Pentium II Processor and Intel 440GX AGPset for more details 2 3 2 GTL Layout Recommendations This section contains the layout recommendations for the GTL signals The layou...

Page 31: ...Update order number 243337 Specifically erratum 42 workaround L1 4 5 Intel strongly recommends running analog simulations using the available I O buffer models together with layout information extract...

Page 32: ...tion space plot show Intel strongly recommends that any traces that fall outside the recommended lengths be simulated to ensure they meeting timing and signal quality specs 2 3 5 Single Processor Syst...

Page 33: ...of design flexibility must be carefully weighed against the cost savings from removing the resistors 2 3 5 2 SET Trace Length Requirements Intel has performed sensitivity analysis on the SET topology...

Page 34: ...delines for VREF distribution and decoupling are contained in P Intel Pentium II Processor Power Distribution Guidelines There are six GTL signals that can be driven by more than one agent simultaneou...

Page 35: ...in this section The heart of the methodology is structured around extensive simulations and analysis prior to board layout This represents a significant departure from traditional design methods The...

Page 36: ...le paths which must be considered Intel Pentium II processor driving an AGPset component AGPset component driving a Intel Pentium II processor Intel Pentium II processor driving a Intel Pentium II pro...

Page 37: ...lated This is necessary to ensure that signal integrity requirements are met Refer to Slot 1 Bus Termination Card Design Guidelines for details 2 3 10 Pre Layout Simulation Sensitivity Analysis After...

Page 38: ...25 4 4 75 5 5 0 0 2 0 4 0 6 0 8 1 1 2 L1 PCa rd 1 to 82 44 0FX Se pa rati on Di stanc e i n L2 PCa rd 2 to 82 44 0FX Se par ati on Dis tance i n D U A L K LA M A TH FLIGH T TIME M AX FT LP C 2 51 inc...

Page 39: ...fined as the difference between the delay of a signal at the input of a receiving agent measured at VREF and the delay at the output pin of the driving agent when driving the GTL reference load Howeve...

Page 40: ...hat it meets the specification at the core NOTE 1 Ringback specifications follow the methodology described in Intel Pentium II Processor at 233 MHz 266 MHz 300 MHz and 333 MHz Datasheet Table 2 5 Syst...

Page 41: ...Recommendations on page 4 1 Tflight max Maximum system flight time Flight time is defined in Section 4 Debug Recommendations on page 4 1 Tco max Maximum driver delay from input clock to output data Tc...

Page 42: ...B skew spec is based on the results of extensive simulations at Intel The Tadj value is based on Intel s experience with systems that use the Intel Pentium Pro processor and Intel Pentium II processor...

Page 43: ...een signal coupling trace spacing and line lengths These routing rules are divided by trace spacing In 1 1 spacing the distance between the traces air gap is the same as the width of the trace In 1 2...

Page 44: ...motherboard AGP signals must be pulled up to VCC3 3 using 8 2K to 10K pull up resistors refer to Section 3 5 1 82443GX Interface on page 3 10 Pull up resistors should be discrete resistors as resisto...

Page 45: ...rongly recommended that the clock spacing be at least four times the trace width to any strobes The clock lines on the motherboard need to be simulated to determine the their proper line length The mo...

Page 46: ...ay Considerations Designing a reliable and high performance memory system will be challenging Careful consideration of motherboard routing and stackup topologies DIMM topology impedance and trace leng...

Page 47: ...a low inductance path for return currents is to provide additional decoupling capacitors next to signal vias It is not possible to route all the MD lines on a single layer As a result some of the MD...

Page 48: ...s Layout Guidelines All signals require careful routing for both min and max trace lengths Figure 2 18 Matching the Reference Planes and Adding Decoupling Capacitor Figure 2 19 4 DIMMs Single or Doubl...

Page 49: ...uidelines Table 2 18 FET Switch DQ Route Example Figure 2 20 Motherboard Model Data MDxx 4 DIMMs v004 0 6 82443GX 1 1 2 0 0 7 2 4 0 3 1 0 0 6 FET SW 82443GX 0 7 2 4 0 4 0 6 DIMM Module 2 DIMM Module 1...

Page 50: ...2 4 6 7 4 DIMMs Figure 2 22 Motherboard Model DQM_A 1 5 4 DIMMs 82443GX 1 0 3 25 0 4 0 6 DIMM Module 1 DIMM Module 2 0 4 0 6 DIMM Module 3 DIMM Module 4 0 4 0 6 82443GX 1 0 3 25 0 4 0 6 DIMM Module 1...

Page 51: ...s Figure 2 24 Motherboard Model DQM_B 1 5 4 DIMMs 82443GX 1 0 3 25 0 4 0 6 DIMM Module 3 DIMM Module 4 Figure 2 25 Motherboard Model CS_A CS_B 4 DIMMs Figure 2 26 Motherboard Model SRAS_A 4 DIMMs 8244...

Page 52: ...e 2 19 Motherboard Model SRAS_B 4 DIMMs Table 2 20 Motherboard Model SCAS_A 4 DIMMs Table 2 21 Motherboard Model SCAS_B 4 DIMMs 82443GX 1 0 3 0 0 4 0 6 DIMM Module 3 DIMM Module 4 82443GX 1 0 3 0 0 4...

Page 53: ...e 2 22 Motherboard Model WE_A 4 DIMMs Table 2 23 Motherboard Model WE_B 4 DIMMs Table 2 24 Motherboard Model MA_A 14 0 4 DIMMs 82443GX 1 0 3 0 0 4 0 6 DIMM Module 1 DIMM Module 2 82443GX 1 0 3 0 0 4 0...

Page 54: ...GPset PCI Bus design is basically the same as the Intel 440BX AGPset The Intel 440GX AGPset supports 5 PCI Bus masters excluding the Intel 440GX AGPset and PIIX4E by the support of 5 PREQ and PGNT lin...

Page 55: ...aced at the corners of the 443GX BGA Package A minimum of four 0 1uF and four 0 01 uF are recommended The system bus AGP PCI and DRAM interface can break out from the BGA package on all four sides Add...

Page 56: ...be maintained between the clock traces and other traces A minimum spacing of 0 018 is recommended for serpentines 2 9 6 2 System Bus Clock Layout System bus clock nets should be routed as point to poi...

Page 57: ...sed to drive DCLKWR at the 82443GX The single clock net should be T d as close as possible to the 82443GX An additional capacitive load of 20pF is also required The capacitor should also be located as...

Page 58: ...ngth Note One driver The signal splits at the 82443GX each half of the trace goes through a 22 Ohm resistor and then to their respective loads If the graphics chip is down on the motherboard the trace...

Page 59: ...3 Design Checklist...

Page 60: ......

Page 61: ...tions RC rise time etc Analysis should be done to determine the minimum maximum values that may be used on an individual signal Engineering judgment should be used to determine the optimal value This...

Page 62: ...t A 31 3 to 82443GX A20M 150 ohm 330 ohm pull up to 2 5V ADS UP Connect to 82443GX DP Connect CPUs and 82443GX AERR Leave as NC AP 1 0 Leave as NC BCLK Connect to CK100 22 ohm series resistor BERR Lea...

Page 63: ...100 22 ohm series resistor PICD 1 0 UP 150 ohm pull up to 2 5V DP Connect CPUs and IOAPIC and 150 ohm pull up to 2 5V PRDY 240 ohm series resistor to ITP PREQ Connected to ITP 330 ohm pull up to 2 5V...

Page 64: ...DP Separate 47 ohm series resistors then hooked together to ITP 1K ohm pull up to 2 5V TRDY UP Connect to 82443GX DP Connect CPUs and 82443GX TRST UP Connect to ITP 680 ohm pull down DP Connect CPUs...

Page 65: ...5 even if an I O APIC is not being used See the Debug Recommendations for further information that may affect these resistor values All CMOS inputs should be pulled up to Vcc2 5 150 ohm to 10K ohm See...

Page 66: ...two regulator outputs together with a wide trace that runs the along the same basic path as the GTL signals beware of crosstalk VREF should be generated at each AGPset component from this combined VTT...

Page 67: ...II processors Each processor site should have an isolated VccCORE power plane Contact your VRM vendor for availability of VRMs with current sharing capabilities if desired The SLOTOCC signal can be u...

Page 68: ...rs 22 ohm series resistors are recommended on the CPU PCI and IOAPIC clock outputs In a UP system clock skew between the 82443GX and the CPU can be reduced by tying the clock driver pins together at t...

Page 69: ...ementation of the 16 bit flip flop for CKE generation for 4 DIMMs GCKE trace length from the 82443GX to the flip flop is recommended to be 1 MIN to 4 MAX CKE trace lengths from the flip flop to the DI...

Page 70: ...00 ohm resistor at both 82443GX and PIIX4E CPURST Connected to CPUs and ITP 240 ohm series resistor CRESET 10K ohm pull up to 3 3V Controls the mux for the CPU strapping signals CSA 5 0 Connect to DIM...

Page 71: ...through 22 ohm series resistor PGNT 4 0 8 2K ohm pull ups to 3 3V Connected to PCI connectors PHLDA 8 2K ohm pull up to 3 3V Connected to PIIX4E PHOLD 8 2K ohm pull up to 3 3V Connected to PIIX4E PIPE...

Page 72: ...internal pull up may prove to be sufficient however the first rev of boards should include the external pull up to be safe 3 5 2 82443GX GTL Bus Interface The Intel 440GX AGPset does not support the...

Page 73: ...ooks to a unique input on the PIIX4E It is recommended that the interrupts be staggered It is also recommended that each PIRQ be programmed to a different IRQ if possible It is the requirement of the...

Page 74: ...1 0 dated Feb 1998 shows pin 81 of the DIMM module is the WP write protect pin for the SPD EEPROM The block diagrams show there is a 47K pull down resistor tied to the WP pin This allows the DIMM man...

Page 75: ...ndors 12 functional units per part requires 6 devices on motherboard 3 6 3 Registered SDRAM There may be power and thermal considerations for registered DIMMs If a design is going to support registere...

Page 76: ...8 2K ohm pull up to 3VSB CONFIG2 8 2K ohm pull down CPURST Leave as a NC CPU_STP GPO17 No connect or connected to CK100 with 10K ohm pull up to 3VSB DACK 7 0 Connect to ISA slots DACK 3 0 also connec...

Page 77: ...CS No connect MEMCS16 Connected to ISA slots 1K ohm pull up to VCC MEMR MEMW Connected to ISA slots and Flash 8 2K ohm pull up to VCC DP Connected to IOAPIC NMI Part of CPU bus frequency circuit 2 7K...

Page 78: ...0 19 Connected to ISA slots Ultra I O Flash LM79 8 2K ohm pull up to VCC DP Connected to IOAPIC SBHE Connect to ISA slots SCS1 Connected to IDE connector through 33 ohm series resistor SCS3 Connected...

Page 79: ...ontrol with 10K ohm pull up to VCC3 SUSB GPO15 No connect SUSC GPO16 Controls ATX power supply SUSCLK No Connect SUS_STAT 2 1 GPO 21 20 No Connect SYSCLK Connect to LM79 and ISA slots TC Connect to SI...

Page 80: ...n the motherboard ground and hard disk drives 3 7 2 2 Motherboard 1 PIIX4E Placement The PIIX4E should be placed as close as possible to the ATA connector s 2 Resistor Location When the distance betwe...

Page 81: ...ement for trace lengths not exceeding 4 inches Note that if the trace length between the PIIX4E and the IDE header exceeds 4 inches the series resistors should be placed within 1 inch of the PIIX4E Th...

Page 82: ...ty The Schottky diode will begin to conduct first therefore carrying the high current VREF can be tied to Vcc in a non 5V tolerant system Tie Vss and Vss USB to ground 3 8 PCI Bus Signals A specific b...

Page 83: ...tion 0 offset B0h B3h The LM79 is connected to the X Bus due to the functionality of the PGCS 1 0 pins on the PIIX4E Table 3 10 Non PIIX4E PCI Signals SIGNAL CONNECTION ACK64 PERR PLOCK REQ64 5V PCI e...

Page 84: ...efore the PIIX4E should be located at close as possible to the ATA connectors to allow the IDE cable to be as long as possible Use ISA reset signal RSTDRV from PIIX4E through a Schmitt trigger for RES...

Page 85: ...Flash Memory Order 292178 This document provides detailed information on flexible layouts Shown below are three of the reference layouts that Intel furnishes to customers These layouts are described...

Page 86: ...tel s flash devices in desktop designs Simplified 2 7 3V 5V Design Considerations Following are general layout guidelines for the Intel s SmartVoltage Smart 5 boot block flash memory 2 4Mbit BV B5 in...

Page 87: ...ignal to drive flash RP to keep device in deep power down during power up only write protection For systems not needing power saving modes Connect BYTE to GND for byte wide mode operation if x16 devic...

Page 88: ...to logic on the board without first going through a Schmitt trigger input to square off and maintain its signal integrity PS_POK logic from the power supply connector can be powered from the core volt...

Page 89: ...logic and pull ups in the path of PWRGOOD to the CPU and PWROK to the PIIX4E with the above exception can be powered from the core supply The PWROK signal to the chipset is a 3V signal The core well p...

Page 90: ...e used Refer to the schematics for implementation details RI can be connected to the modem if this feature is used To implement ring indicate as a wake event the source driving the RI signal must be p...

Page 91: ...With the exception of GPI1 all unused GPIx inputs on the PIIX4E should be tied high through pull up resistors 8 2K ohm 10K ohm to a power plane Tying directly to the power plane is also acceptable GP...

Page 92: ...r from the PIIX4 reduces its effectiveness 3 17 82093AA IOAPIC An I O APIC is required for a DP system and is optional for a UP system The I O APIC is a 5V device All Vcc pins must be connected to 5V...

Page 93: ...hat selects between APIC OS IRQ20 and PIC OS IRQ9 so the BIOS can properly report to the OS which interrupt is assigned to the SCI The SMI signal from the PIIX4 PIIX4E should be connected directly to...

Page 94: ...ic is needed to ensure that at least 4 clock cycles occur between ALTRST and ISOLATE assertion The distance between Magnetics i e Cat 3 or Cat 5 wire and RJ 45 connector should be kept to less than on...

Page 95: ...Intel Pentium II processor as early as possible in the POST during system boot up The BIOS update signature mechanism should be used to validate that the BIOS Update has been accepted by the processo...

Page 96: ...erature measured 0 3 above the center of the fan See the Intel Pentium II Processor Datasheet for the TPH Specification Verify that all major components including the 82443GX can be cooled the way the...

Page 97: ...especially if the layout guideline recommendations in this document are not followed It is recommended that simulations be performed to ensure proper timings and signal integrity is met especially if...

Page 98: ...t run in parallel separate them on different layers with a well decoupled power or ground plane If they must run parallel on the same layer then separate the traces by a minimum of 25 mils Proper oper...

Page 99: ...4 Debug Recommendations...

Page 100: ......

Page 101: ...a way to connect your logic analyzer to signals on the processor system bus They are available from two logic analyzer vendors Hewlett Packard Co for their HP 16500B series logic analyzers Contact you...

Page 102: ...2 5 FLOTHERM Model A FLOTHERM Model is available for the Intel Pentium II processor 4 3 Debug Features These suggestions are for debug purposes only on initial prototype systems and are not required f...

Page 103: ...nput current leakage input timings etc The resulting values may conflict As a result of the extra loading the following compromise pull ups to Vcc 2 5 are recommended The actual value required by your...

Page 104: ...ection See the Integration tools chapter of the processor datasheet for schematics and a signal checklist Be sure it is the proper 0 050 x 100 1 27mm x 4mm spacing connector Provide the capability to...

Page 105: ...ed the tool in this file This file needs to change based on what components are in the boundary scan chain In DP systems the processor with PREQ0 and PRDY0 is considered processor 0 even if it is not...

Page 106: ...the deassertion of RESET if BIST is not configured to run If BIST is configured to run BNR will continue to toggle until BIST completion After BNR stops toggling the PICD 1 0 signals begin the MP init...

Page 107: ...5 Third Party Vendors...

Page 108: ......

Page 109: ...vailability pricing and compatibility 5 1 Processors Table 5 1 Slot 1 Connector Supplier Contact Phone AMP Incorporated Mike Mullen 717 592 2352 Framatome Connectors Leonard Dore 717 767 8006 Foxconn...

Page 110: ...aurice Lee 886 2 7164822 x233 Taiwan 510 770 0660 x111 LinFinity Andrew Stewart 714 372 8383 Raytheon Hubert Engle Brechten 415 962 7982 Semtech European CNDA Alan Moore 805 498 2111 x291 VXI Electron...

Page 111: ...ardware monitor will be used to monitor voltage regulation and fan RPM 5 2 3 FET Switches 4 DIMM FET Design Intel is recommending that OEMs contact the particular vendor for pricing and availability o...

Page 112: ...n mechanism retention mechanism attach mount and heat sink supports 5 3 3 Heat sinks Public information see Intel Pentium Processor Support Components Web page Mechanical dimensions are public an MP C...

Page 113: ...A Reference Design Schematics...

Page 114: ......

Page 115: ...he EMI signals A thermal sensor the MAX 1617 ME which connects to an internal processor diode has been included to monitor processor temperature Intel Pentium II Slot 1 processor connector part 2 4 an...

Page 116: ...ws the 82443GX component Memory and System Data Bus Interfaces GTL_REF signal are also shown on this page Ideally the GTL_REF signals should be decoupled separately and as close as possible to the 824...

Page 117: ...vides logic level transitions for the PIIX4E Note the placement requirements for the capacitors and series resistors at the bottom left Flash BIOS Component 27 This page shows the 28F002BC T Flash BIO...

Page 118: ...s speed and quieting the system Pull up and Pull down Resistors 34 35 These pages show pull up and pull down resistors for PCI signals PIIX4E Slot 1 CMOS ISA and AGP signals Also shown are spare gates...

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