Intel 440GX, Design Manual

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Intel
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440GX AGPset Design Guide A-1
Intel
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440GX AGPset Platform Reference Design
Intel
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440GX AGPset Platform Reference
Design A
This section describes the DP/Intel
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440GX AGPset 4-DIMM Reference Design Schematics. The
description of each schematic page is named by the logic block shown on that page. The numbers
after the schematic page name list the page number of the dual processor design.
Cover Sheet 1
The Cover Sheet shows the Schematic page titles, page numbers and disclaimers.
Block Diagram 2
This page shows a block diagram overview of the Intel
®
Pentium
®
II / Intel
®
440GX AGPset
system design. Also included is a device table listing every major component in the design, its
reference designator, and location.
Intel
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Pentium
®
II Slot 1 processor connector (part 1) 3 and 5
This page shows the first part of the Slot 1 connector (up to the key). SLP# connection comes
directly from the PIIX4E. Intel recommends placing 0 ohm resistors on the EMI signals. A thermal
sensor (the MAX 1617 ME) which connects to an internal processor diode has been included to
monitor processor temperature.
Intel
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Pentium
®
II Slot 1 processor connector (part 2) 4 and 6
This page shows the remaining part Slot 1connector. Also shown are the optional connections for
overriding the VID pins from the processor.
Clock Synthesizer and ITP connector 7
This page shows the new clock synthesizer component the CK100 plus recommended decoupling.
The clock synthesizer components must meet all of the system bus, PCI and other system clock
requirements. Several vendors offer components that can be used in this design.
This page also shows the In Target Probe (ITP) Connector. The ITP connector is recommended in
order to use the In Target Probe tool available from Intel and other tool vendors for Intel
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Pentium
®
II Processor based platform debug.
Note: Some logic analyzer vendors also support the use of the ITP connector. This connector is optional.
It is recommended to design these headers into the system for initial system debug and
development, and leave the connector footprints unpopulated for production.