LYNX Manual RA02
2.1.4 Timing
Diagrams
IPX-VGA120-L, IPX-VGA210-L
In the single mode each line consists of 12 empty pixels (E1 – E12),
followed by 24 masked pixels used for black reference (R1 – R24),
followed by 4 buffer pixels (B1 – B4), followed by 640 active data
pixels (D1 – D640), followed by 4 buffer pixels (B1 – B4), and
followed by another 24 masked dark pixels (R1 – R24) – Figure 2.6..
In dual mode each line consists of 12 empty pixels (E1 – E12),
followed by 24 masked pixels used for black reference (R1 – R24),
followed by 4 buffer pixels (B1 – B4), followed by 320 active data
pixels – Figure 2.7. The data is sampled on the rising edge of the
clock, and the LVAL (line valid) signal is active only during the active
pixels. Each frame (for all modes) consists of 35.4 us vertical frame
timing, followed by 4 masked dark lines (RL1 – RL4), followed by 4
buffer lines (BL1 – BL4), followed by 480 active lines (DL1 –
DL480), and followed by 4 buffer lines (BL1 – BL4). During each
frame the FVAL (frame valid) signal is active only during the active
lines (DL1 – DL480) – Figure 2.8.
DATA
LVAL
12 empty
pixels
24 dark
pixels
640 active
data pixels
300 ns
600 ns
16000 ns
4 buffer
pixels
100 ns
4 buffer
pixels
100 ns
24 dark
pixels
600 ns
- 0 -
E1
E12 R1
R24
B1
B4
D1
D640
B1
B4
R1
R24
- 0 -
Figure 2.6 - Single Output Line Timing (IPX-VGA120/210-L)
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