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NANO-ULT5 SBC
Page 61
4.7.2 Clear CMOS Button
CN Label:
J_CMOS1
CN Type:
Button
CN Location:
See
If the NANO-ULT5 fails to boot due to improper BIOS settings, use the button to clear the
CMOS data and reset the system BIOS information.
The location of the clear CMOS button is shown in
Figure 4-11: Clear CMOS Button Location
Summary of Contents for NANO-ULT5
Page 2: ...NANO ULT5 SBC Page II Revision Date Version Changes May 21 2019 1 00 Initial release...
Page 14: ......
Page 15: ...NANO ULT5 SBC Page 1 Chapter 1 1 Introduction...
Page 24: ...NANO ULT5 SBC Page 10 Chapter 2 2 Unpacking...
Page 28: ...NANO ULT5 SBC Page 14 Chapter 3 3 Connectors...
Page 66: ...NANO ULT5 SBC Page 52 Chapter 4 4 Installation...
Page 89: ...NANO ULT5 SBC Page 75 Chapter 5 5 BIOS...
Page 128: ...NANO ULT5 SBC Page 114 Chapter 6 6 Software Drivers...
Page 132: ...NANO ULT5 SBC Page 118 Appendix A A Regulatory Compliance...
Page 134: ...NANO ULT5 SBC Page 120 B Product Disposal Appendix B...
Page 136: ...NANO ULT5 SBC Page 122 Appendix C C BIOS Menu Options...
Page 139: ...NANO ULT5 SBC Page 125 Appendix D D Digital I O Interface...
Page 142: ...NANO ULT5 SBC Page 128 Appendix E E Watchdog Timer...
Page 145: ...NANO ULT5 SBC Page 131 Appendix F F Hazardous Materials Disclosure...