ICS SB686P Series, Product Manual

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Manual Number: 40110-005-2 Page 32
C/BE[7::4]# (optional)
Bus Command and Byte Enables are multiplexed on the same pins. During an address phase
(when using the DAC command and when REQ64# is asserted), the actual bus command is
transferred on C/BE[7::4]#; otherwise, these bits are reserved and indeterminate. During a data
phase, C/BE[7::4]# are byte enables indicating which byte lanes carry meaningful data when
REQ64# and ACK64# are both asserted. C/BE4# applies to byte4 and C/BE7# applies to byte7
CLK
Clock provides timing for all transactions on PCI and is an input to every PCI device.
DEVSEL#
Device Select, when actively driven, indicates that the driving device has decoded its address as
the target of the current access. As an input, DEVSEL# indicates whether any device on the bus
has been selected.
FRAME#
Cycle Frame is an interface control pin which is driven by the current master to indicate the
beginning and duration of an access. When FRAME# is asserted, data transfers continue; when
it is deserted, the transaction is in the final data phase.
GNT#
Grant indicates to the agent that access to the bus has been granted. This is a point to point signal.
Every master has its own GNT#.
IDSEL
Initialization Device Select is used as a chip select during configuration read and write
transactions.
INTA#, INTB#, INTC#, INTD# (optional)
Interrupts on PCI are optional and defined as “level sensitive,” asserted low (negative true), using
open drain output drivers. PCI defines one interrupt for a single function and up to four interrupt
lines for a multifunction device or connector.
Interrupt A is used to request an interrupt. For a single function device, only INTA# may be used,
while the other three interrupt lines have no meaning.
Interrupt B, Interrupt C and Interrupt D are used to request additional interrupts and only have
meaning on a multifunction device.
IRDY#
Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data
phase of the transaction. IRDY# is used in conjunction with TRDY#. During a write, IRDY#
indicates that valid data is present on AD[31::0]. During a read, it indicates that the master is
prepared to accept data.