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Manual Number: 40110-005-2
Page 22
M16# (I)
M16# Chip Select signals the system board if the present data transfer is a 1wait-state, 16bit,
memory cycle. It must be derived from the decode of LA[23::17]. M16# should be driven with
an open collector or tri-state driver capable of sinking 20 mAmps.
Master16# (I)
Master16# is used with a DRQ line to gain control of the system. A processor or DMA controller
on the I/O channel may issue a DRQ to a DMA channel in cascade mode and receive a DAK#.
Upon receiving the DAK#, an I/O microprocessor may pull Master16# low, which will allow it
to control the system address, data, and control lines (a condition known as tri-state). After
Master16# is low, the I/O microprocessor must wait one system clock period before driving the
address and data lines, and two clock periods before issuing a Read or Write command. If this
signal is held low for more than 15microseconds, system memory may be lost because of a lack
of refresh.
NOWS# (I)
The No Wait State (NOWS#) signal tells the microprocessor that it can complete the present bus
cycle without inserting any additional wait cycles. In order to run a memory cycle to a 16-bit
device without wait cycles, NOWS# is derived from an address decode gated with a Read or
Write command. In order to run a memory cycle to an 8-bit device with a minimum of two wait
states, NOWS# should be driven active on system clock after the Read or Write command is
active gated with the address decode for the device. Memory Read and Write commands to a
8-bit device are active on the falling edge of the system clock. NOWS# is active low and should
be driven with an open collector or tristate driver capable of sinking 20 mAmps.
OSC (O)
Oscillator (OSC) is a high-speed clock with a 70-nanosecond period (14.31818 MHz). This
signal is not synchronous with the system clock. It has a 50% duty cycle.
REFRESH# (I/O)
The REFRESH# signal is used to indicate a refresh cycle and can be driven by a microprocessor
on the I/O channel.
RESDRV (O)
Reset Drive (RESDRV) is used to reset or initialize system logic at power-up time or during a
low line-voltage outage. This signal is active high.
SA[19::0] (I/O)
Address bits SA[19::0] are used to address memory and I/O devices within the system. These
twenty address lines, in addition to LA[23::17], allow access of up to 16MB of memory.
SA[19::0] are gated on the system bus when BALE is high and are latched on the falling edge
of BALE. These signals are generated by the microprocessor or DMA Controller. They also may
be driven by other microprocessors or DMA controllers that reside on the I/O channel.
Summary of Contents for SB686P Series
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