ICS SB686P Series, Product Manual

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Manual Number: 40110-005-2 Page 26
PCI Local Bus
PCI Overview
The PCI (Peripheral Component Interconnect) Local Bus is a high performance, 32-bit or 64-bit
bus with multiplexed address and data lines. It is intended for use as an interconnect mechanism
between highly integrated peripheral controller components, peripheral add-in boards and proces-
sor/memory systems.
The “local bus” moves peripheral functions with high bandwidth requirements closer to the system’s
processor bus and can produce substantial performance gains with graphical user interfaces (GUI’s)
and other high bandwidth functions (i.e., full motion video, SCSI, LAN’s, etc.). The PCI Local
Bus accommodates future system requirements and is applicable across multiple platforms and
architectures.
The PCI component and add-in card interface is processor independent, enabling an efficient tran-
sition to future processor generations, by bridges or by direct integration, and use with multiple
processor architectures.
Processor independence allows the PCI Local Bus to be optimized for I/O functions, enables con-
current operation of the local bus with the processor/memory subsystem, and accommodates mul-
tiple high performance peripherals in addition to graphics. Movement to enhanced video and
multimedia displays and other high bandwidth I/O will continue to increase local bus bandwidth
requirements. A transparent 64-bit extension of the 32-bit data and address buses is defined, dou-
bling the bus bandwidth and offering forward and backward compatibility of 32-bit (132MB/s
peak) and 64-bit (264MB/s peak) PCI Local Bus peripherals.
PCI Local Bus Signal Definition
The PCI interface requires a minimum of 47 pins for a target-only device and 49 pins for a master
to handle data and addressing, interface control, arbitration and system functions. The diagram
below shows the pins in functional groups, with required pins on the left side and optional pins on
the right side.