Manual Number: 40110-005-2
Page 23
SBHE# (I/O)
System Bus High Enable (SBHE#) indicates a transfer of data on the upper byte of the data bus,
D[15::8]. 16-bit devices use SBHE# to condition data bus buffers tied to D[15::8].
SMRDC# (O), MRDC# (I/O)
These signals instruct the memory devices to drive data onto the data bus. SMRDC# is active
only when the memory decode is within the low 1MB of memory space. MRDC# is active on
all memory read cycles. MRDC# may be driven by any microprocessor or DMA controller in
the system. SMRDC is derived from MRDC# and the decode of the low 1MB of memory. When
a microprocessor on the I/O channel wishes to drive MRDC#, it must have the address lines valid
on the bus for one system clock period before driving MRDC# active. Both signals are active
low.
SMWTC# (O), MWTC# (I/O)
These signals instruct the memory devices to store the data present on the data bus. SMWTC#
is active only when the memory decode is within the low 1MB of the memory space. MWTC#
is active on all memory write cycles. MWTC# may be driven by any microprocessor or DMA
controller in the system. SMWTC# is derived from MWTC# and the decode of the low 1MB
of memory. When a microprocessor on the I/O channel wishes to drive MWTC#, it must have
the address lines valid on the bus for one system clock period before driving MWTC# active.
Both signals are active low.
T-C (O)
Terminal Count (T-C) provides a pulse when the terminal count for any DMA channel is reached.
Summary of Contents for SB686P Series
Page 2: ...Page ii...
Page 14: ...Manual Number 40110 005 2 Page 4...
Page 27: ...Manual Number 40110 005 2 Page 17 ISA Bus Pin Numbering...
Page 37: ...Manual Number 40110 005 2 Page 27 PCI Local Bus Pin Numbering...
Page 56: ...Manual Number 40110 005 2 Page 46 This page intentionally left blank...
Page 80: ...Manual Number 40110 005 2 Page 70 This page intentionally left blank...
Page 122: ......
Page 124: ......
Page 126: ......