ICS SB686P Series, Product Manual

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Manual Number: 40110-005-2 Page 7
PCI Ultra SCSI Interface
The SCSI interface is a PCI Bus Master device which supports Ultra SCSI 16-bit data transfer
up to 40MB per second and bursts data to the host at full PCI speeds. Active termination is
provided with terminator voltage protected by self-resetting fuses. The SCSI controller is an
Adaptec 7880.
PCI Enhanced IDE Interface (DUAL)
A high performance PCI Bus Master EIDE interface is capable of supporting up to four IDE Type
4 disk drives in a master/slave configuration. With LBA settings in the BIOS parameters, disk
drives greater than 528MB are supported. The interface supports transfer rates to 16.7MB per
second.
Floppy Drive Interface
The processor board supports two floppy disk drives. Drives can be 360K to 2.88MB, in any
combination.
Serial Interface
Two high-speed FIFO (16C550) serial ports with independently programmable baud rates are
supported. Each port has BIOS selectable addressing. A filtered connector is provided to
minimize FCC interference.
Enhanced Parallel Interface
The processor board provides a PC/AT compatible bidirectional parallel port and supports
enhanced parallel port (EPP) mode and extended capabilities port (ECP) mode. The ECP mode
is IEEE 1284 compliant. The parallel port has BIOS selectable addressing.
PS/2 Mouse Interface
The processor board provides compatibility with a PS/2-type mouse. The mouse connection can
be made by using either the PS/2 mouse header or the bracket mounted PS/2 mouse mini DIN
connector.
Watchdog Timer
The watchdog timer is a hardware timer which resets the processor board if the timer is not
refreshed by software periodically. The timer is typically used to restart a system in which an
application becomes hung on an external event. When the application is hung, it no longer
refreshes the timer. The watchdog timer then times out and resets the processor board.
The watchdog timer has two levels of enable. First, the watchdog timer jumper must be moved
to the “enabled” position, which puts the watchdog timer under software control.
The second level is done in two phases. First, access to the watchdog timer gate, ADRx, via a
user-defined I/O port must be enabled and configured in registers 3, 8 and 9 of the FDC37C665GT
configuration registers. Bits 7 and 2 of register 3 set ADRx mode, while registers 8 and 9 define
the I/O port address used to write a 0 or 1 to the ADRx bit. The ADRx bit is physically wired
to the gate that is enabled by the jumper.