Service Guide
A-18
ECC Memory Component Test
This test is identical to the main memory components test but it is applied to the ECC
memory components.
Error Correction Mechanism Test
This test checks the hardware mechanisms enabling the detection of and the correction of
single bit errors when working with the main memory. It also detects double errors.
Memory Refresh Mechanism Test
This test is performed by all the processors. It checks the mechanism embedded in the SMC
ASIC enabling it to refresh the main memory. This test checks the SMC ASIC hardware
partially. This test contains the following sub-test.
Refresh Mechanism Test
In this test, the memory address is calculated first. Then two
complementary patterns are written in the work area. Then a read
and compare operation is done. If an error is detected, a Memory
read error is displayed. The refresh mechanism is checked in the
following manner.
A read operation is done on another location (other than the one
previously read) until the delay time is over. Then the previous
location is once again read, to verify the presence of the same data
(this is possible, only if the chip is refreshed periodically).
Main Memory full Test
This test performs the most complete test on the main memory, using the Knaizuk-Hartmann
algorithm.
This test is very long (about 20 minutes) when the memory capacity to be checked is large
(2GB). So, it is performed only as an extended test or under the OFF line test monitor
control.
Summary of Contents for 7012 G Series
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