ropes to support 4 Lower Bus Adapter (LBA) chips. Each LBA chip interfaces with the SBA in the
zx1 chip, through one or multiple rope connections, as follows:
•
One LBA chip uses a single rope connection (used by core I/O) to support a single 32-bit PCI
bus running at 33 MHz;
•
One LBA chip use a single-rope connection (used by controller) to support one 64-bit PCI-X
bus running at 66 MHz;
•
Two LBA chips use a dual rope connection (used by LAN and FibreChannel controllers) to
support individual 64-bit PCI-X buses running at 133 MHz;
Enclosure Information
This installation document covers only the HP Integrity BL860c server blade, and does not include
any specific server blade enclosure information. For server blade enclosure information, go to the
HP website at:
http://h71028.www7.hp.com/enterprise/cache/316735-0-0-0-121.html
Cooling Subsystem
The server blade does not contain any fans. Cooling is handled by the enclosure.
Troubleshooting Communications Modules
This subsection provides information on troubleshooting issues with the internal PCI-X buses.
I/O Subsystem Behaviors
The main role of the I/O subsystem is to transfer blocks of data and instruction words between
physical shared memory and virtual memory (server disks/disk array). The server boot is the first
time blocks of data and instructions words are transferred into physical shared memory from a
local disk/DVD, or from a remote disk on another server through multiple LAN transfers. This
process is referred to as Direct Memory Access (DMA), and is initiated by I/O devices located in
core I/O or on I/O device controllers, and does not involve any processors.
A secondary function of the I/O subsystem is to transfer four bytes of data between the internal
registers within each processor core, and the internal control and store registers in the zx1/PDH
/Local Bus Adapters (LBAs), and device controller chips. This process is called programmed I/O,
and is initiated by any processor executing external LOAD/STORE instructions.
NOTE:
System firmware and the HP-UX kernel both use the programmed I/O method to initiate
direct memory access (DMA) transfers.
Customer Messaging Policy
•
Always point the customer to the SEL for any action from low level I/O subsystem faults. IPMI
events in SEL/FPL provide the logical ACPI path of the suspect I/O subsystem FRU. Use
Table 26
to determine the physical device controller.
•
Some diagnostic messages are reported for high level I/O subsystem errors; all fatal I/O
subsystem errors cause global MCAs. (Note that HP-UX provides its own path with the physical
rope number of the suspect I/O subsystem FRU. Use
Table 26
to determine the physical device
controller.)
Table 26 Rope-to-ACPI Paths
Logical ACPI Path
Physical Rope #
PCI Bus
Acpi(HWP0002,PNP0A00,0)/Pci(1 | 0)
0
Slow core iLO 2 MP @ 33MHz
Acpi(HWP0002,PNP0A03,0)/Pci(1 | 1)
104 Troubleshooting
