Holtek HT82K75REW, Manual

Page: 70 / 103

HT82M75REW/HT82K75REW
Rev. 1.00 70 June 11, 2010
·
SREG0x30 - RXSR: RX MAC Status Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name RXFFFULL WRFF1
¾
RXFFOVFL RXCRCERR
¾ ¾ ¾
Type R R R R R R R R
POR 0 0 0 0 0 0 0 0
Bit 7 RXFFFULL : RX FIFO Full
1: RX FIFO is not available for data receiving
0: RX FIFO is available for data receiving (default)
Bit 6 WRFF1 : RX FIFO Status
1: Packet is ready in RX FIFO 1
0: Packet is ready in RX FIFO 0 (default)
Bit 5 Reserved: maintain as
²
0b0
²
Bit 4 RXFFOVFL : RX FIFO Overflow
1: RX FIFO overflows
0: (default) RX FIFO not overflow
Bit 3 RXCRCERR : RX CRC Error
1: RX CRC error
0: RX CRC is correct (default)
Bit 2~0 Reserved: maintain as
²
0b000
²
·
SREG0x31 - ISRSTS: Interrupt Status Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name
¾
WAKEIF
¾ ¾
RXIF
¾ ¾
TXNIF
Type R RC R R RC R R RC
POR 0 0 0 0 0 0 0 0
Bit 7 Reserved: maintain as
²
0b0
²
Bit 6 WAKEIF : Wake-up Alert Interrupt
1: A wake-up interrupt occurred
0: No wake-up alert interrupt occurred (default)
This bit is cleared to 0 when the register is read.
Bit 5-4 Reserved: maintain as
²
0b00
²
Bit 3 RXIF : RX FIFO Reception Interrupt
1: A RX FIFO reception interrupt occurred
0: No RX FIFO reception interrupt occurred (default)
This bit is cleared to 0 when the register is read.
Bit 2-1 Reserved: maintain as
²
0b00
²
Bit 0 TXNIF : TX FIFO Normal Transmission Interrupt
1: TX FIFO normal transmission interrupt occurred
0: No TX FIFO normal transmission interrupt occurred (default)
This bit is cleared to
²
0
²
when the register is read.
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