HT82M75REW/HT82K75REW
Rev. 1.00
42
June 11, 2010
EEPROM Data Memory Functional Description
The embedded EEPROM Data Memory is an I2C type
device and therefore operates using a two wire serial
bus. It has a capacity is 1K organized into a structure of
128 8-bit words and contains the information or data im-
portant for user.
EEPROM Data Memory Internal Connection
In addition to the pins described above there are other
MCU to EEPROM Data Memory interconnecting lines
that are described in the above EEPROM Pin Descrip-
tion table. Note that the SDA and SCL lines are internal
connected to the MCU I/O pins respectively and are not
bonded to external pins.
Accessing the EEPROM Data Memory
The two I2C lines are the Serial Clock line, SCL, and the
Serial Data line SDA. The SDA and SCL pins are inter-
nal connected to the host MCU I/O pins. Normal I/O con-
trol software instructions are used to control the reading
and writing operations on the EEPROM Data Memory.
·
Serial data - SDA
The SDA line is the bidirectional EEPROM serial data
line which is controlled by the host MCU I/O pin. The
host MCU should configure this I/O pin as input or out-
put dynamically opposite to the data direction of the
EEPROM. The SDA line is an internal line and not
connected to an output pin.
·
Serial clock - SCL
The SCL line is the EEPROM serial clock input line
which is controlled by the host MCU I/O pin. The host
MCU should configure this I/O pin connected to the
SCL line as output pin. The SCL line is an internal line
and not connected to an output pin. The SCL input
clocks data into the EEPROM on its positive edge and
clocks data out of the EEPROM on its negative edge.
·
Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in the
data line while the clock line is high will be interpreted
as a START or STOP condition.
·
Start condition
A high-to-low transition of SDA with SCL high will be
interpreted as a start condition which must precede
any other command - refer to the Start and Stop Defi-
nition Timing diagram.
·
Stop condition
A low-to-high transition of SDA with SCL high will be
interpreted as a stop condition. After a read sequence
the stop command will place the EEPROM in a
standby power mode - refer to Start and Stop Defini-
tion Timing Diagram.
·
Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re-
ceived each word. This happens during the ninth clock
cycle.
Device Addressing
All EEPROM devices require an 8-bit device address
word following a start condition to enable the EEPROM
for read or write operations. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits. Refer to the diagram showing
the Device Address. This is common to all the EEPROM
devices. The next three bits are all zero bits.
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
SDA
SCL
EEPROM
VDDP
VSSP
I/O.x
I/O.y
VDD
VSS
MCU
VDD
VDD
Dual VDD/Single VSS Power Supply
MCU to EEPROM Internal Connection
SDA
SCL
EEPROM
VDDP
VSSP
I/O.x
I/O.y
VDD
VSS
MCU
VDD
VDD
Dual VDD / Dual VSS Power Supply
MCU to EEPROM Internal Connection
S C L
S D A
D a t a a l l o w e d
t o c h a n g e
A d d r e s s o r
a c k n o w l e d g e
v a l i d
S t o p
c o n d i t i o n
S t a r t
c o n d i t i o n
N o A C K
s t a t e
Start and Stop Definition Timing Diagram
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