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HT82M75REW/HT82K75REW

Rev. 1.00

13

June 11, 2010

¨

The three methods are shown as follows: The in-
structions

²

TABRDC [m]

²

(the current page, one

page=256words), where the table location is de-
fined by TBLP (07H) in the current page. And the
configuration option TBHP is disabled (default).

¨

The instructions

²

TABRDC [m]

²

, where the table lo-

cation is defined by registers TBLP (07H) and
TBHP (01FH). And the configuration option TBHP
is enabled.

¨

The instructions

²

TABRDL [m]

²

, where the table lo-

cation is defined by register TBLP (07H) in the last
page (F00H~FFFH).

Only the destination of the lower-order byte in the ta-
ble is well-defined, the other bits of the table word are
transferred to the lower portion of TBLH, and the re-
maining 1-bit words are read as

²

0

²

. The Table

Higher-order byte register (TBLH) is read only. The ta-
ble pointer (TBLP, TBHP) is a read/write register (07H,
1FH), which indicates the table location. Before ac-
cessing the table, the location must be placed in the
TBLP and TBHP (If the configuration option TBHP is
disabled, the value in TBHP has no effect). The TBLH
is read only and cannot be restored. If the main rou-
tine and the ISR (Interrupt Service Routine) both em-
ploy the table read instruction, the contents of the
TBLH in the
main routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main rou-
tine and the ISR simultaneously should be avoided.
However, if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt
should be disabled prior to the table read instruction. It

will not be enabled until the TBLH has been backed
up. All table related instructions require two cycles to
complete the operation. These areas may function as
normal program memory depending on the require-
ments.
Once TBHP is enabled, the instruction

²

TABRDC [m]

²

reads the ROM data as defined by TBLP and TBHP
value. Otherwise, the configuration option TBHP is
disabled, the instruction

²

TABRDC [m]

²

reads the

ROM data as defined by TBLP and the current pro-
gram counter bits.

Table Program Example

The following example shows how the table pointer and
t a b l e d a t a i s d e f i n e d a n d r e t r i e v e d f r o m t h e
microcontroller. This example uses raw table data lo-
cated in the last page which is stored there using the
ORG statement. The value at this ORG statement is

²

F00H

²

which refers to the start address of the last page

within the 4K Program Memory of device. The table

pointer is setup here to have an initial value of

²

06H

²

.

This will ensure that the first data read from the data ta-

ble will be at the Program Memory address

²

F06H

²

or 6

locations after the start of the last page. Note that the
value for the table pointer is referenced to the first ad-

dress of the present page if the

²

TABRDC [m]

²

instruc-

tion is being used. The high byte of the table data which
in this case is equal to zero will be transferred to the

TBLH register automatically when the

²

TABRDL [m]

²

in-

struction is executed.

P r o g r a m

M e m o r y

P r o g r a m C o u n t e r

H i g h B y t e

T B L P

T B L H

S p e c i f i e d b y [ m ]

T a b l e C o n t e n t s H i g h B y t e

T a b l e C o n t e n t s L o w B y t e

Table Read

-

TBLP only

P r o g r a m

M e m o r y

T B L H

S p e c i f i e d b y [ m ]

H i g h B y t e o f T a b l e C o n t e n t s

L o w B y t e o f T a b l e C o n t e n t s

T B L P

T B H P

Table Read

-

TBLP/TBHP

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Summary of Contents for HT82K75REW

Page 1: ...wo bit to define microcontroller system clock fSYS 1 fSYS 2 fSYS 4 All instructions executed in one or two machine cycles Table read instructions 63 powerful instructions 6 level subroutine nesting Bit manipulation instruction Program Memory 4K 15 Data Memory 128 8 160 8 Watchdog Timer function Up to 40 bidirectional I O lines with pull high options All I O pins have falling and rising edge wake u...

Page 2: ...7 4 6 4 5 4 4 4 3 4 2 4 1 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 H T 8 2 K 7 5 R E W 6 4 L Q F P A P A 6 P A 7 P D 0 P D 1 P D 2 P D 3 P D 4 P D 5 P D 6 P D 7 G P I O 2 G N D _ D G P I O 1 G P I O 0 V D D _ D V D D _ 2 V 2 P B 3 ...

Page 3: ... high or Wake up CMOS NMO S Bidirectional 8 bit input output port Each pin can be configured as a wake up input both falling and rising edge by a configuration option Soft ware instructions determine if the pin is a CMOS output or Schmitt Trigger input Configuration options determine if the pins have pull high resistors Also a configuration option determines if the PC pins are CMOS output type or ...

Page 4: ...also used as an external TX RX switch control GPIO2 I O External General Purpose digital I O It is also used as an external Power Amplifier P A enable control VDD_D I External RF transceiver digital circuit power supply GND_D I External RF transceiver digital circuit power supply VDD_2V2 O External RF transceiver DC DC output voltage It cannot be used VDD_3V I External RF transceiver 3V input for ...

Page 5: ...ectively for the HT82M75REW and HT82K75REW devices Absolute Maximum Ratings Supply Voltage VSS 0 3V to VSS 6 0V Storage Temperature 50 C to 125 C Input Voltage VSS 0 3V to VDD 0 3V Operating Temperature 40 C to 85 C IOL Total 150mA IOH Total 100mA Total Power Dissipation 500mW Note These are stress ratings only Stresses exceeding the range specified under Absolute Maximum Ratings may cause substan...

Page 6: ...Min Max fSK SCL Clock Frequency 100 kHz tHIGH Clock High Time 4000 ns tLOW Clock Low Time 4700 ns tr SDA and SCL Rise Time Note 1000 ns tf SDA and SCL Fall Time Note 300 ns tHD STA START Condition Hold Time After this period the first clock pulse is generated 4000 ns tSU STA START Condition Setup Time Only relevant for repeated START condition 4000 ns tHD DAT Data Input Hold Time 0 ns tSU DAT Data...

Page 7: ... Time out Period 1024 tRCSYS Power On Reset Characteristics Ta 25 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions IPOR Operating current 1 8V 3 3V 1 0 mA RRVDD VDD Rise Rate to Ensure Power on Reset Without 0 1mF between VDD and VSS 0 05 V ms VPOR Maximum VDD Start Voltage to Ensure Power on Reset Without 0 1mF between VDD and VSS Ta 25 C 0 9 1 5 V tPOR Power on Reset Low Pulse ...

Page 8: ...rates in Active TX mode or Active RX mode If the RF Transceiver is active either ITX or IRX should be added to calculate the relevant operating current of the device for different operating mode To calculate the standby current for the whole device the standby current shown above including ISTB IDS and IPD should be taken into account for different Power Saving Mode RF Transceiver A C Characterist...

Page 9: ...trol range 36 dB TX gain control resolution 0 1 0 5 dB Carrier suppression 30 dBc TX spectrum mask for O QPSK signal Offset frequency 3 5 MHz At 0 dBm output power 30 dBm 20 dBc TX EVM 30 Synthesizer VDD 3V Ta 25 C LO frequency 2 445GHz 250 Kbps DC DC Off Parameters Test Conditions Min Typ Max Unit PLL Stable Time 130 ms PLL Programming resolution 1 MHz HT82M75REW HT82K75REW Rev 1 00 9 June 11 201...

Page 10: ...uction cycles the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle The exception to this are instructions where the contents of the Program Counter are changed such as subroutine calls or jumps in which case the instruction will take one more instruction cycle to execute For instructions involving branches such as jump or call ...

Page 11: ... Pointer SP and is neither readable nor writeable At a subroutine call or interrupt acknowledge signal the con tents of the Program Counter are pushed onto the stack At the end of a subroutine or an interrupt routine sig naled by a return instruction RET or RETI the Program Counter is restored to its previous value from the stack After a device reset the Stack Pointer will point to the top of the ...

Page 12: ...ters Special Vectors Within the Program Memory certain locations are re served for special usage such as reset and interrupts Location 000H This vector is reserved for use by the device reset for program initialisation After a device reset is initiated the program will jump to this location and begin execu tion Location 004H This vector is used by serial interface When 8 bits of data have been rec...

Page 13: ...led until the TBLH has been backed up All table related instructions require two cycles to complete the operation These areas may function as normal program memory depending on the require ments Once TBHP is enabled the instruction TABRDC m reads the ROM data as defined by TBLP and TBHP value Otherwise the configuration option TBHP is disabled the instruction TABRDC m reads the ROM data as defined...

Page 14: ...high byte register TBLH org F00h sets initial address of last page dc 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 01Ah 01Bh Because the TBLH register is a read only register and cannot be restored care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use the table read instructions If using the table read instructions the Interrupt Service Routines may change the v...

Page 15: ...oller programs require an area of read write memory where temporary data can be stored and retrieved for use later It is this area of RAM memory that is known as General Purpose Data Memory This area of Data Memory is fully accessible by the user pro gram for both read and write operations By using the SET m i and CLR m i instructions individual bits can be set or reset under program control givin...

Page 16: ... H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H U n u s e d r e a d a s 0 0 D F H G e n e r a l P u r p o s e D a t a M e m o r y 1 6 0 B y t e s I A R 0 M P 0 I A R 1 M P 1 A C C P C L T B L P T B L H W D T S S T A T U S I N T C T M R H T M R L T M R C P T R P A P A C P B P B C P C P C C P D P D C P E P E C C T L R T B H P S P I R S B C R S B D R 4 0 H 2 0 H...

Page 17: ... MP1 register pair can ac cess data from all of the data banks if the Data Memory is divided into 2 or more banks As the Indirect Ad dressing Registers are not physically implemented reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indi rectly will result in no operation Memory Pointer MP0 MP1 For all devices two Memory Pointers known as...

Page 18: ...ration option TBHP is disabled the instruction TABRDC m reads the ROM data as defined by TBLP and the current program counter bits Status Register STATUS This 8 bit register contains the zero flag Z carry flag C auxiliary carry flag AC overflow flag OV power down flag PDF and watchdog time out flag TO These arithmetic logical operation and system manage ment flags are used to record the status and...

Page 19: ...that port With each I O port there is an asso ciated control register known as PAC PBC etc also mapped to specific addresses with the Data Memory Input Output Ports Holtek microcontrollers offer considerable flexibility on their I O ports With the input or output designation of ev ery pin fully under user program control pull high op tions for all ports and Wake up option for all I O pins the user...

Page 20: ...nput the corresponding control bits in the timer control reg ister must be correctly set For applications that do not require an external timer input this pin can be used as a normal I O pin Note that if used as a normal I O pin the timer mode control bits in the timer control register must select the timer mode which has an internal clock source to prevent the input pin from interfering with the ...

Page 21: ...lue is stored The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the PA2 TMR pin The timer will count from the initial value loaded by the preload regis ter to the full count value of FFFFH at which point the timer overflows and an internal interrupt signal gener ated The timer value will then be reset with the initia...

Page 22: ... When the timer is full and overflows the timer will be reset to the value already loaded into the preload reg ister and continue counting If the timer interrupt is en abled an interrupt signal will also be generated The timer interrupt can be disabled by ensuring that the ETI bit in the INTC register is cleared to zero T i m e r E v e n t C o u n t e r C o n t r o l R e g i s t e r b 7 T E T O N ...

Page 23: ...ON bit will be automati cally reset to zero and the timer will stop counting If the TE bit is high the timer will begin counting once a low to high transition has been received on the PA2 TMR pin and stop counting when the PA2 TMR pin returns to its original low level As before the TON bit will be automat ically reset to zero and the timer will stop counting It is important to note that in the Pul...

Page 24: ... same applies if the timer is configured to be in the event counting mode which again is an external event and not synchronised with the internal system or timer clock When the Timer Event Counter is read or if data is writ ten to the preload register the clock is inhibited to avoid errors however as this may result in a counting error this should be taken into account by the programmer Care must ...

Page 25: ...errupt can be enabled or disabled Also when an interrupt occurs the request flag will be set by the microcontroller The global enable bit if cleared to zero will disable all interrupts Interrupt Operation A Timer Event Counter overflow will generate an inter rupt request by setting its corresponding request flag if its interrupt enable bit is set When this happens the Program Counter which stores ...

Page 26: ... capability of waking up the processor when in the Power Down Mode Only the Program Counter is pushed onto the stack If the contents of the accumulator or status register are al tered by the interrupt service program which may cor rupt the desired control sequence then the contents should be saved in advance A u t o m a t i c a l l y C l e a r e d b y I S R M a n u a l l y S e t o r C l e a r e d ...

Page 27: ...n reset also ensures that certain other registers are preset to known conditions All the I O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs Although the microcontroller has an internal RC reset function if the VDD power supply rise time is not fast enough or does not stabilise quickly at power on the internal reset function may ...

Page 28: ...flag will be set to 1 Refer to the A C Characteristics for tSST details Reset Initial Conditions The different types of reset described affect the reset flags in different ways These flags known as PDF and TO are located in the status register and are controlled by various microcontroller operations such as the Power Down function or Watchdog Timer The reset flags are shown in the table TO PDF RES...

Page 29: ... 00 0 1 00 0 1 00 0 1 00 0 1 uu u u PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 1111 1111 ...

Page 30: ...de signer if the power consumption is to be minimised Special attention must be made to the I O pins on the device All high impedance input pins must be con nected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption Care must also be taken with the loads which are connected to I O pins which are setup as outp...

Page 31: ...lock source of the WDT comes from the in ternal WDT oscillator and its clock period may vary with VDD temperature and process variation The WDT clock is further divided by an internal 6 stage counter followed by a 7 stage prescaler to obtain longer WDT time out period selected by the WDT prescaler rate se lection bits WS2 WS0 in the associated WDT register known as WDTS There is only one instructi...

Page 32: ...ll be woken up by Period Timer Register overflow Once the MCU is woken up by the period timer the CNT_WK bit of the wake up Register is set to 1 Bit No Function Name R W Description 0 7 Period Timer R W The Period Timer is the time interval generator with one second as a unit If the bits 7 0 are equal to 00H the MCU will be woken up by one of the wake up source mentioned in Wake up Section except ...

Page 33: ... to enable the DC DC circuit If the configuration option is selected to disable the LVR function or the DC_ctrl bit is set to 1 to disable the DC DC circuit then the LVR function will be dis abled If the LVR function is enabled by appropriate set ting of the configuration option and software control bit as mentioned above then the LVR still works even if the MCU enters into the Power Down Mode It ...

Page 34: ...ll be in an unknown condition while the SBCR register will default to the condition below CKS M1 M0 SBEN MLS CSEN WCOL TRF 0 1 1 0 0 0 0 0 Note that data written to the SBDR register will only be written to the TXRX buffer whereas data read from the SBDR register will actual be read from the register SPI Bus Enable Disable To enable the bus the SBEN bit should be set high then wait for data to be ...

Page 35: ... t a r t a n d s t a r t SPI Block Diagram Note WCOL set by SPI cleared by users CSEN enable disable chip selection function pin master mode 1 0 with without SCS output function Slave mode 1 0 with without SCS input control function SBEN enable disable serial bus 0 initialise all status flags when SBEN 0 all status flags should be initialised when SBEN 1 all SPI related function pins should stay a...

Page 36: ... MSB or LSB first this must be same as the Slave device Step 4 Setup the SBEN bit in the SBCR control register to enable the SPI interface Step 5 For write operations write the data to the SBDR register which will actually place the data into the TXRX buffer Then use the SCK and SCS lines to output the data Goto to step 6 For read operations the data transferred in on the SDI line will be stored i...

Page 37: ...from continuing The bit will be set high by the Serial Interface but has to be cleared by the user application program The overall function of the WCOL bit can be disabled or enabled by a configuration option Programming Considerations When the device is placed into the Power Down Mode note that data reception and transmission will continue The TRF bit is used to generate an interrupt when the dat...

Page 38: ...D 5 D 1 D 6 D 0 D 7 S D I S C K S P I _ C P O L 0 S C K S P I _ C P O L 1 S P I _ m o d e 0 S P I _ m o d e 1 S D I S D O S C K S P I _ C P O L 1 S C S S P I _ C S E N 1 S C K S P I _ C P O L 0 S B E N C S E N 1 a n d w r i t e d a t a t o S B D R S B E N 1 C S E N 0 a n d w r i t e d a t a t o S B D R I O m o d e S B E N C S E N 1 a n d w r i t e d a t a t o S B D R S B E N 1 C S E N 0 a n d w r ...

Page 39: ... F T r a n s f e r F i n i s h e d E N D M a s t e r o r S l a v e M a s t e r S l a v e A A M 1 M 0 1 1 S P I T r a n s f e r M 1 M 0 0 0 0 1 1 0 S e l e c t c l o c k C K S C o n f i g u r e C S E N a n d M L S T r a n s m i s s i o n C o m p l e t e d T R F 1 Y e s Y e s N o N o SPI Transfer Control Flowchart Downloaded from Elcodis com electronic components distributor ...

Page 40: ...isable 10 WDT clock source enable disable for normal mode 11 PB wake up by bit Wake up or non wake up 12 PC wake up by bit Wake up or non wake up 13 PC output type CMOS NMOS 14 PB0 output type CMOS NMOS 15 PD pull high by nibble pull high or non pull high 16 PE pull high by nibble pull high or non pull high 17 PD wake up by nibble wake up or non wake up 18 PE wake up by nibble wake up or non wake ...

Page 41: ... Operation Random Address Read Operation Sequential Address Read Operation EEPROM Memory Overview An area of EEPROM which stands for Electrically Eras able Programmable Read Only Memory is contained within the device This type of memory is non volatile with data retention even after power is removed and is useful for storing information such as product identifica tion numbers calibration values us...

Page 42: ...busy During data transfer the data line must remain stable whenever the clock line is high Changes in the data line while the clock line is high will be interpreted as a START or STOP condition Start condition A high to low transition of SDA with SCL high will be interpreted as a start condition which must precede any other command refer to the Start and Stop Defi nition Timing diagram Stop condit...

Page 43: ...he last byte of the last memory page to the first byte of the first page Once the device address with the read write select bit set to one is clocked in and ac knowledged by the EEPROM the current address data word is serially clocked out The microcontroller should respond a No ACK High signal and a follow ing stop condition Random read Arandom read requires a dummy byte write sequence to load in ...

Page 44: ... A C K S t o p S t a r t S D A A C K N o A C K S A C K D A T A S D e v i c e a d d r e s s S t a r t Random Read Timing P D e v i c e a d d r e s s D A T A n S t o p S t a r t S D A A C K S A C K D A T A n 1 D A T A n x N o A C K Sequential Read Timing t f t L O W t r t H I G H t S U S T A t H D S T A t S P t H D D A T t S U D A T t S U S T O t B U F V a l i d V a l i d S C L S D A S D A O U T t A...

Page 45: ...utomatic ACK response and FCS check 62 byte TX FIFO Dual 64 byte RX FIFOs Various power saving modes Simple four wire SPI interface RF Transceiver Applications Home Building Factory Automation PC Peripheral RF Remote Controller Consumer Electronics 2 way Medium Data Rate Applications RF Transceiver Overview The device contains a 2 4 GHz RF transceiver with a Baseband MAC block The RF transceiver c...

Page 46: ...er volt age controlled oscillator VCO and phase locked loop PLL It uses advanced radio architecture to minimize the external component count and the power consump tion The Baseband MAC block provides the hardware architecture for both MAC and PHY layers It mainly consists of TX RX control and digital signal processing module Interconnection between the MCU and the RF Transceiver is implemented by ...

Page 47: ...f this external capacitor is 47pF Under 1M bps turbo mode user can use the same pro gram settings of MAC and all MAC functions are re mained the same Compare with 250k bps mode in 1M bps mode signal bandwidth is extended to 8MHz The packet includes a 6 bytes PHY header and a 7 63 bytes PHY payload The 6 bytes PHY header includes 4 bytes of preamble 1 byte of start of frame delimiter SFD and 1 byte...

Page 48: ...frame back after determining that the received frame is valid The bit 1 of FC field is 0 for data frame The length of payload field is variable from 0 to 56 bytes The frame check sequence FCS is calculated over the address field FC field and the payload The polynomial is de gree 16 Acknowledgement Frame The length of acknowledgement frame is always 5 bytes Bit 1 of FC field is 1 for ACK frame The ...

Page 49: ... If Ping Pong RX mode is enabled by SREG0x34 0 RXMAC automatically switches between RXFIFO0 and RXFIFO1 to store incoming frame whenever a new packet comes When the MCU host reads the long ad dress memory 0x300H the RXMAC will change the flag of SREG0x34 1 automatically For manually controlled RX operation if the value of the flag SREG0x34 1 is 0 the RXFIFO0 shall be read Otherwise the RXFIFO1 sha...

Page 50: ...eplied ACK frame is not received the transmitter automatically resends the packet until the maximum retransmission times specified in SREG0x1B 7 4 are reached To uti lize the function properly the corresponding registers of both transmitting and receiving sides need to be set cor rectly Auto retransmission on TX Side To automatically retransmit a packet when an ACK is not received SREG0x1B 2 is re...

Page 51: ...aseband RF parameter settings etc The registers are divided into two types ac cording to addressing mode as listed below Short address register 6 bit short addressing mode register total 64 registers Long address register 10 bit long addressing mode register total 128 registers Short address registers are accessed by short address ing mode with valid addresses ranging from 0x00H to 0x3FH Long addr...

Page 52: ...XCON r r TXONTS3 TXONTS2 TXONTS1 TXONTS0 r r 1000 1000 0x1B TXTRIG TXRTYN3 TXRTYN2 TXRTYN1 TXRTYN0 r TXACKREQ r TXTRIG 0011 0000 0x22 WAKECTL IMMWAKE REGWAKE r r r r r r 0100 0000 0x24 TXSR TXRETRY3 TXRETRY2 TXRETRY1 TXRETRY0 r r r TXNS 0000 0000 0x26 GATECLK r r SPISYNC r r ENTXM r r 0000 0000 0x2A SOFTRST r r r r r r RSTBB RSTMAC 0000 0000 0x2E TXPEMISP TXPET3 TXPET2 TXPET1 TXPET0 r r r r 0111 0...

Page 53: ...000 0x211 IRQCTRL r r r r r r IRQCTRL r 0000 0000 0x22F TESTMODE MPSPI r r r r TESTMODE2 TESTMODE1 TESTMODE0 0010 1000 0x23D GPIODIR r r GDIRCTRL2 GDIRCTRL1 GDIRCTRL0 GPIO2DIR GPIO1DIR GPIO0DIR 0011 1111 0x23E GPIO r r r r r GPIO2 GPIO1 GPIO0 0000 0000 0x250 RFCTRL50 r r r DCPOC DCOPC3 DCOPC2 DCOPC1 DCOPC0 0000 0000 0x251 RFCTRL51 DCOPC5 DCOPC4 r r r r r r 0000 0000 0x252 RFCTRL52 SLCTRL6 SLCTRL5 ...

Page 54: ...ss sensor network applications require low power consumption to lengthen battery life Typical battery powered device is required to be operated over years without replacing its battery The RF Transceiver achieves low active current consumption of both the dig ital and the RF analog circuits by controlling the supply voltage and using low power architecture The RF Transceiver has four power saving ...

Page 55: ... Registers and FIFOs data are not retained a wake up input sig nal can wake up the RF Transceiver IDLE mode is rarely used because the device should at least always turns on its RX circuit to capture the on air RF signals The only difference between STANDBY mode and DEEP_SLEEP mode is the power status of the sleep clock To wake the RF Transceiver up the MCU host has to control the time of sleep pr...

Page 56: ...edge of SCLK SI hold time tHD 25 ns The minimum time data must be held at SI after the positive edge of SCLK Rise time tRISE 25 ns The maximum rise time for SCLK and SEN Fall time tFALL 25 ns The maximum fall time for SCLK and SEN SPI Timing Diagram The following figures show the timing diagrams for the short and long addressing mode respectively The MCU SPI master will initiate a read or write op...

Page 57: ...se refer to the following sec tion named External Power Amplifier Configuration for details Interrupt Signal The RF Transceiver provides an interrupt output pin named INT and the polarity of the interrupt signal is selectable The RF Transceiver issues interrupts to the MCU host on three possible events If one of the three events happens the RF Transceiver sets the corre sponding status bit in SREG...

Page 58: ...XON time 94 SREG 0x2E TXPEMISP VCO calibration period 95 LREG 0x200 RFCTL0 RF optimized control 01 LREG 0x201 RFCTL1 RF optimized control 02 LREG 0x202 RFCTL2 RF optimized control E0 LREG 0x204 RFCTL4 RF optimized control 06 LREG 0x206 RFCTL6 RF optimized control C0 1M bps LREG 0x207 RFCTL7 RF optimized control F0 1M bps LREG 0x208 RFCTL8 RF optimized control 8C LREG 0x23D GPIODIR For Setting GPIO...

Page 59: ... VCOTXOPT0 r r PLLOPT2 PLLOPT1 PLLOPT0 r 0000 0000 0x274 RFCTRL74 PACEN0 PACTRL0 2 PACTRL0 1 PACTRL0 0 PACEN1 PACTRL1 2 PACTRL1 1 PACTRL1 0 1100 1010 0x275 RFCTRL75 r r r r SCLKOPT3 SCLKOPT2 SCLKOPT1 SCLKOPT0 0001 0101 0x276 RFCTRL76 r r r r r SCLKOPT6 SCLKOPT5 SCLKOPT4 0000 0001 Change RF Channel Procedure The RF Transceiver operates in 2 4GHz ISM band The operating frequency is divided into 16 c...

Page 60: ... in RX mode the GPIO0 and GPIO1 will be pulled LOW and GPIO2 will be pulled HIGH The status of GPIO pins are automatically changed corresponding to TX RX mode of the RF Transceiver TX mode GPIO0 GPIO1 GPIO2 HIGH HIGH LOW RX mode GPIO0 GPIO1 GPIO2 LOW HIGH HIGH Registers associated with External Power Amplifier Configuration Addr File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on PO...

Page 61: ...o 0 it means that the transmis sion is successful and the ACK was received The number of times of the retransmission can be read at SREG0x24 7 4 If SREG0x24 0 is equal to 1 it means that the transmission failed and ACK was not received Registers associated with Typical TX Operation Addr File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR 0x1B TXTRIG TXRTYN3 TXRTYN2 TXRTYN1 TXRTY...

Page 62: ...G0x277 3 2 to 10 for enable sleep voltage automatically controlled by internal circuit Set LREG0x253 6 5 to 11 to connect the FIFO power and digital circuit power to ground If the internal connected interrupt line named WAKE is going to be used to wake the RF Transceiver up the configura tion for WAKE line should be included Refer to the following WAKE Line Wake up Section for details The on chip ...

Page 63: ...leepclock is 10000ns Set SREG0x36 4 3 and SREG0x35 6 0 to 0x12 Register Trigger Wake up User can wake the RF Transceiver up from STANDBY and DEEP_SLEEP modes by simply setting SREG0x22 7 6 to 11 When the RF Transceiver is woken up by Register trigger the following steps shall be executed to complete the opera tion Wait the RF Transceiver issues a wake up interrupt The related wake up interrupt fla...

Page 64: ...iver has Battery Monitor function and the procedure to enable the Battery Monitor function is described as below Set the battery monitor threshold value at LREG0x205 7 4 Enable the battery monitor by setting the LREG0x206 3 to the value 1 Read the battery low indicator at SREG0x34 5 If this bit is set it means that the supply voltage is lower than the bat tery monitor threshold specified by LREG0x...

Page 65: ...maintain as 0b00000 SREG0x03 AUINFL Acknowledgement User Information Low Byte Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name AUINF7 AUINF6 AUINF5 AUINF4 AUINF3 AUINF2 AUINF1 AUINF0 Type R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 AUINF 7 0 16 bit User Information of Acknowledgement frame Low Byte SREG0x04 AUINFH Acknowledgement User Information High Byte Bit Bit 7 Bit 6 B...

Page 66: ...ADR30 DADR29 DADR28 DADR27 DADR26 DADR25 DADR24 Type R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 DADR 31 24 32 bit Address of the RF Transceiver SREG0x0D RXFLUSH Receive FIFO Flush Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name PTX RXFLUSH Type R R R R R R W R WT POR 0 1 1 0 0 0 0 0 Bit 7 Reserved maintain as 0b0 Bit 6 5 Reserved maintain as 0b11 Bit 4 3 Reserved maintain...

Page 67: ... 0 Name PAONTS3 PAONTS2 PAONTS1 PAONTS0 Type R R R R W R W R W R W R POR 0 0 0 0 0 0 1 0 Bit 7 5 Reserved maintain as 0b000 Bit 4 1 PAONTS 3 0 Power Amplifier Settling Time to begin packet transmission 0001 default 0100 optimized do not change Bit 0 Reserved maintain as 0b0 SREG0x18 TXCON Transmitter Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name TXONTS3 TXONTS2 TXONTS1 ...

Page 68: ...rdware SREG0x22 WAKECTL Wake up Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name IMMWAKE REGWAKE Type R W WT R R R R R R POR 0 1 0 0 0 0 0 0 Bit 7 IMMWAKE Immediate Wake up Mode Enable bit 1 enable immediate Wake up Mode 0 disable immediate Wake up Mode default Bit 6 REGWAKE Register Triggered Wake up bit 1 To wake the RF Transceiver up Bit is automatically to 0 by hardwar...

Page 69: ... Type R R R R R R WT WT POR 0 0 0 0 0 0 0 0 Bit 7 2 Reserved Maintain as 0b000000 Bit 1 RSTBB Baseband Reset 1 reset baseband circuitry Initialization is not needed after RSTBB reset Bit is automatically cleared to 0 by hardware Bit 0 RSTMAC MAC and Short Long Addressing Registers Reset 1 Reset MAC circuitry and Short Long Addressing Registers Initialization is needed after RSTMAC reset Bit is aut...

Page 70: ...SRSTS Interrupt Status Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name WAKEIF RXIF TXNIF Type R RC R R RC R R RC POR 0 0 0 0 0 0 0 0 Bit 7 Reserved maintain as 0b0 Bit 6 WAKEIF Wake up Alert Interrupt 1 A wake up interrupt occurred 0 No wake up alert interrupt occurred default This bit is cleared to 0 when the register is read Bit 5 4 Reserved maintain as 0b00 Bit 3 RXIF RX FIFO ...

Page 71: ...POR 0 0 0 0 0 0 0 0 Bit 7 6 Reserved Maintain as 0b00 Bit 5 BATIND Battery Low Indicator 1 battery voltage is lower than the threshold voltage specified by the LREG0x205 7 4 0 battery voltage is higher than the threshold voltage specified by the LREG0x205 7 4 default Bit 4 2 Reserved Maintain as 0b000 Bit 1 RDFF1 RX FIFO Selected to Read 1 read data from RX FIFO 1 0 read data from RX FIFO 0 defaul...

Page 72: ...ry to calibrate Bit 1 0 Reserved Maintain as 0b00 SREG0x38 BBREG0 Baseband Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name TURBO Type R R R R R R R R W POR 1 0 0 0 0 0 0 1 Bit 7 1 Reserved Maintain as 0b1000000 Bit 0 TURBO Turbo Mode Select 1 1M bps Turbo Mode default 0 250k bps Normal Mode RF Transceiver Long Addressing Registers LREG0x200 LREG0x27F 0x200 RFCTRL0 0x211 IRQCTL 0x...

Page 73: ...MHz 1011 channel 22 2460MHz 1100 channel 23 2465MHz 1101 channel 24 2470MHz 1110 channel 25 2475MHz 1111 channel 26 2480MHz Bit 3 0 Reserved Maintain as 0b0001 LREG0x201 RFCTRL1 RF Control Register 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name VCORX1 VCORX0 Type R R R R R R R W R W POR 0 0 0 0 0 0 0 1 Bit 7 2 Reserved Maintain as 0b000000 Bit 1 0 VCORX 1 0 RX VC 01 default 10 optimize...

Page 74: ...dBm 01111 2 8 dBm 10000 3 1 dBm 10001 3 3 dBm 10010 3 6 dBm 10011 3 8 dBm 10100 4 2 dBm 10101 4 4 dBm 10110 4 7 dBm 10111 5 0 dBm 11000 5 3 dBm 11001 5 7 dBm 11010 6 2 dBm 11011 6 5 dBm 11100 6 9 dBm 11101 7 4 dBm 11110 7 9 dBm 11111 8 3 dBm TX Output Power Configuration Summary table TX Output Power Register Control LREG0x253 3 0 LREG0x274 7 0 LREG0x203 7 3 TX Output Power 00 C6 for DC DC OFF 000...

Page 75: ...R R R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 3 Reserved Maintain as 0b00000 Bit 2 RXFCO RX Filter Calibration output 1 optimized do not change 0 default Bit 1 0 RXD2O 1 0 RX Divide by 2 option 00 default 10 optimized do not change LREG0x205 RFCTRL5 RF Control Register 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name BATTH3 BATTH2 BATTH1 BATTH0 Type R W R W R W R W R R R R POR 0 0 0 0 0 0 0 ...

Page 76: ...FC2 RX Filter Control 2 1 For 1M bps Turbo Mode 0 For 250k bps Normal Mode default Bit 3 0 Reserved Maintain as 0b0000 LREG0x208 RFCTRL8 RF Control Register 8 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name TXD2CO1 TXD2CO0 Type R W R W R R R R R R POR 0 0 0 0 1 1 0 0 Bit 7 6 TXD2CO 1 0 TX Divide by 2 Option 00 default 10 Optimized do not change Bit 5 0 Reserved Maintain as 0b001100 LREG0x...

Page 77: ...R 0 0 0 0 0 0 0 0 Bit 7 SLPCALRDY Sleep Clock Calibration Ready 1 Sleep Clock Calibration counter is ready to be read 0 Not Ready default Bit 6 5 Reserved Maintain as 0b00 Bit 4 SLPCALEN Sleep Clock Calibration Enable 1 Starts the Sleep Clock Calibration counter Bit is automatically cleared to 0 by hardware Bit 3 0 SLPCAL 19 16 Sleep Clock Calibration Counter bit 19 16 A 20 bit calibration counter...

Page 78: ...DIRCTRL0 GPIO2DIR GPIO1DIR GPIO0DIR Type R R R W R W R W R W R W R W POR 0 0 1 1 1 1 1 1 Bit 7 6 Reserved Maintain as 0b00 Bit 5 3 GDIRCTRL 2 0 GPIO Direction Control 000 Optimized do not change 111 default Bit 2 GPIO2DIR General Purpose I O GPIO2 Direction 1 Input default 0 Output Bit 1 GPIO1DIR General Purpose I O GPIO1 Direction 1 Input default 0 Output Bit 0 GPIO0DIR General Purpose I O GPIO0 ...

Page 79: ...5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name DCOPC5 DCOPC4 Type R W R W R W R W R R R R POR 0 0 0 0 0 0 0 0 Bit 7 6 DCOPC 5 4 DC DC Converter Optimization Control 00 default 11 Optimized do not change Bit 5 0 Reserved Maintain as 0b000000 LREG0x252 RFCTRL52 RF Control Register 52 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SLCTRL6 SLCTRL5 SLCTRL4 SLCTRL3 SLCTRL2 SLCTRL1 SLCTRL0 32MXCTRL Type ...

Page 80: ...eiver is in Power Saving Mode 1 GND 0 VDD default Bit 5 DIGITALPS Digital Power while Sleep 1 GND 0 VDD default Bit 4 P32MXE Partial 32MHz Clock Enable 1 Enable 0 Disable default Bit 3 PACEN2 Power Amplifier Control 2 Enable 1 Enable 0 Disable default Bit 2 0 PACTRL2 2 0 Power Amplifier Control 2 000 default PACTRL2 2 0 is for 1st stage Power Amplifier current fine tuning Please follow the TX Outp...

Page 81: ... 0011100 2428 MHz 0011101 2429 MHz 0011110 2430 MHz 0011111 2431 MHz 0100000 2432 MHz 0100001 2433 MHz 0100010 2434 MHz 0100011 2435 MHz 0100100 2436 MHz 0100101 2437 MHz 0100110 2438 MHz 0100111 2439 MHz 0101000 2440 MHz 0101001 2441 MHz 0101010 2442 MHz 0101011 2443 MHz 0101100 2444 MHz 0101101 2445 MHz 0101110 2446 MHz 0101111 2447 MHz 0110000 2448 MHz 0110001 2449 MHz 0110010 2450 MHz 0110011 ...

Page 82: ...d for DC DC Converter Bypass Bit 0 Reserved Maintain as 0b0 LREG0x274 RFCTRL74 RF Control Register 74 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name PAC0EN PACTRL0 2 PACTRL0 1 PACTRL0 0 PAC1EN PACTRL1 2 PACTRL1 1 PACTRL1 0 Type R W R W R W R W R W R W R W R W POR 1 1 0 0 1 0 1 0 Bit 7 PAC0EN Power Amplifier Control 0 Enable 1 Enable default 0 Disable Bit 6 4 PACTRL0 2 0 Power Amplifier C...

Page 83: ...in as 0b00000 Bit 2 0 SCLKOPT 6 4 Sleep Clock Optimization 111 Optimized do not change 001 default LREG0x277 RFCTRL77 RF Control Register 77 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SLPSEL1 SLPSEL0 SLPVCTRL1 SLPVCTRL0 SLPVSEL1 SLPVSEL0 Type R R R W R W R W R W R W R W POR 0 0 0 0 1 0 0 0 Bit 7 6 Reserved Maintain as 0b00 Bit 5 4 SLPSEL 1 0 Power Saving Mode Selection 00 default Sta...

Page 84: ...n not be set to 1 1 as slave mode Although the SPI mode selection bits M1 M0 can be set to 0 0 0 1 and 1 0 along with the SPI clock source selection bit CKS to force the host MCU SPI interface to operate as Master SPI with different baud rate there are some limitations on the maximum SPI clock speed that can be selected to be suitable for the RF Transceiver slave SPI clock speed As the maximum RF ...

Page 85: ... enable control bit SPI_CSEN of the Master SPI should be set to 0 then the master SPI SCS line will lose the SCS line characteristics and be configured as a general purpose I O line SPI_CSEN software CSEN enable control bit in SPIR Register Bit Bit 5 Name SPI_CSEN Setting value 0 0 the software CSEN function is disabled and the SCS line is configured as an I O line Finally set the SPI_EN bit to 1 ...

Page 86: ...DD_3V 0 1uF 100uH 0 1uF VB VDD_3V VDD_BG VDD_GR XTAL_N XTAL_P VDD_PLL VDD_CP VDD_VCO LOOP_C VDD_RF1 RF_N NC VDD_RF2 PB1 PB2 PB3 PB4 PA0 PA1 PA2 PA3 PA4 PA5 VSS VDD VDD BAT_IN LX RES PA7 PA6 PB7 PB6 PB5 GPIO2 GPIO1 GPIO0 VDD_D VDD_2V2 VDD_A VSSLX 10nF VCC_3V 47uF BEAD 15pF 32M 15pF VCC_3V 4 7uF 47pF 10nF 10nF 1uF 47pF VCC_3V 47pF 47pF 10nF 6 8nH 4 7nH 5 6nH 0 47pF 0 47pF ANT 1pF 1 2nH RF_P Download...

Page 87: ..._A DB4 XTAL_N XTAL_P GND_PLL VDD_PLL VDD_CP VDD_VCO DB5 DB5 LOOP_C VDD_RF1 N C RF_P RF_N N C VDD_RF2 PC1 PC0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 LX VSSLX BAT_IN VSS VDD RES PA0 PA1 PA2 TMR PA3 PA4 PA5 VDD_3V VDD_3V 100K 0 1uF 0 1uF 47uF 220uF VDD_3V VCC_3V 10nF 0 1uF VCC_3V 0 1uF VCC_3V 4 7uF VCC_3V 0 1uF VCC_3V 47pF 10nF 47pF 15pF 15pF 10nF 1uF 47pF VCC_3V VCC_3V 47pF 10nF...

Page 88: ...ion mnemonics to enable the necessary arithmetic to be carried out Care must be taken to en sure correct handling of carry and borrow data when re sults exceed 255 for addition and less than 0 for subtraction The increment and decrement instructions INC INCA DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified Logical and Rota...

Page 89: ...ary The following table depicts a summary of the instruction set categorised according to function and can be con sulted as a basic instruction reference using the follow ing listed conventions Table conventions x Bits immediate data m Data Memory address A Accumulator i 0 7 number of bits addr Program memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A m ADDM A m ADD A x ADC...

Page 90: ...Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Table Read TABRDC m 4 TABRDC m 5 TABRDL m Read ROM code locate by TBLP and TBHP to data memory and TBLH Read ROM code current page to data memory and TBLH Read table last page to TBLH and Data Memory 2...

Page 91: ...ration ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C AND A m Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op eration T...

Page 92: ... Description The TO PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this instruction works in conjunc tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect Re petitively executing this instruction without alternately executing...

Page 93: ...lue of 6 will be added to the high nibble Essentially the decimal conversion is performed by add ing 00H 06H 60H or 66H depending on the Accumulator and flag conditions Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H or m ACC 66H Affected ...

Page 94: ...Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator Operation ACC m Affected flag s None MOV A x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator Operation ACC x Affected flag s None MOV m A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Me...

Page 95: ...peration Program Counter Stack ACC x Affected flag s None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re enabled by set ting the EMI bit EMI is the master interrupt global enable bit If an interrupt was pending when the RETI instruction is executed the pending Interrupt routine will be processed be fore returning to the main program ...

Page 96: ...ry right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro tated into bit 7 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i m i 1 i 0 6 ACC 7 m 0 Affected flag s None RRC m Rotate Data Memory right through Carry Description The contents of the specified Da...

Page 97: ...esult is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it is a two cycle instruction If the result is not 0 the program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SDZA m Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified ...

Page 98: ...d it is a two cycle instruction If the result is 0 the program proceeds with the following instruction Operation Skip if m i 0 Affected flag s None SUB A m Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator The result is stored in the Accumulator Note that if the result of subtraction is negative the C flag will be cleared to 0 ot...

Page 99: ...llowing instruc tion Operation Skip if m 0 Affected flag s None SZA m Skip if Data Memory is 0 with data movement to ACC Description The contents of the specified Data Memory are copied to the Accumulator If the value is zero the following instruction is skipped As this requires the insertion of a dummy instruc tion while the next instruction is fetched it is a two cycle instruction If the result ...

Page 100: ...by the table pointer TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None XOR A m Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op eration The result is stored in the Accumulator Operation ACC ACC XOR m Affected fl...

Page 101: ...D2 0 173 0 177 0 179 E2 0 173 0 177 0 179 L 0 014 0 016 0 018 K 0 008 Symbol Dimensions in mm Min Nom Max A 0 80 0 85 0 90 A1 0 00 0 02 0 05 A3 0 20 b 0 18 0 25 0 30 D 6 00 E 6 00 e 0 50 D2 4 40 4 50 4 55 E2 4 40 4 50 4 55 L 0 35 0 40 0 45 K 0 20 HT82M75REW HT82K75REW Rev 1 00 101 June 11 2010 D E e b A 1 A 3 A D 2 L E 2 K 1 1 0 1 1 2 0 2 1 3 0 3 1 4 0 Downloaded from Elcodis com electronic compon...

Page 102: ...0 45 0 75 K 0 09 0 20 a 0 7 Symbol Dimensions in inch Min Nom Max A 0 350 0 358 B 0 272 0 280 C 0 350 0 358 D 0 272 0 280 E 0 016 F 0 005 0 009 G 0 053 0 057 H 0 063 I 0 002 0 006 J 0 018 0 030 K 0 004 0 008 a 0 7 HT82M75REW HT82K75REW Rev 1 00 102 June 11 2010 4 8 4 9 3 3 3 2 6 4 1 1 6 1 7 A B C D E F G H I J K a Downloaded from Elcodis com electronic components distributor ...

Page 103: ... 9885 http www holtek com Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC The information appearing in this Data Sheet is believed to be accurate at the time of publication However Holtek as sumes no responsibility arising from the use of the specifications described The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that s...

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