HT82M75REW/HT82K75REW
Rev. 1.00
56
June 11, 2010
¨
SPI Addressing Format
MSB of addressing frame indicates the addressing mode of the packet. The length of address field is 6 or 10 bits for
short and long addressing mode respectively. Bit 0 is a one-bit read/write indicator.
¨
SPI Characteristics
Parameter
Symbol
Min.
Max.
Unit
Conditions
SCLK, clock frequency
f
SCLK
¾
5
MHz
SCLK low pulse duration
t
CL
100
¾
ns
The minimum time SCLK must be low.
SCLK high pulse duration
t
CH
100
¾
ns
The minimum time SCLK must be high.
SEN setup time
t
SP
100
¾
ns
The minimum time SEN must be low before the first
positive edge of SCLK.
SEN hold time
t
NS
100
¾
ns
The minimum time SEN must be held low after the
last negative edge of SCLK.
SI setup
t
SD
25
¾
ns
The minimum time data must be ready at SI, before
the positive edge of SCLK
SI hold time
t
HD
25
¾
ns
The minimum time data must be held at SI, after the
positive edge of SCLK.
Rise time
t
RISE
¾
25
ns
The maximum rise time for SCLK and SEN.
Fall time
t
FALL
¾
25
ns
The maximum fall time for SCLK and SEN.
¨
SPI Timing Diagram
The following figures show the timing diagrams for the short and long addressing mode respectively. The MCU SPI
master will initiate a read or write operation by asserting the interface enable signal SEN to low, toggling SCLK and
sent the address field by SI. The interface enable signal SEN should be high when a transaction is completed.
SPI Addressing Format
A6 A5
A3
A4
A2 A1 0
0
D
R
7 D
R
6
D
R
4
D
R
5
D
R
3 D
R
2
D
R
0
D
R
1
0 A6
X
A6 A5
A3
A4
A2 A1 1
0
D
w
6
D
w
4
D
w
5
D
w
3 D
w
2
D
w
0
D
w
1
0
D
w
7
SCLK
SEN
SI
SO
SI
SO
t
SP
t
SD
t
HD
t
CH
t
CL
t
NS
read short address data
write short address data
A5 A4 A3 A2 A1 0
X
D
R
7
D
R
5
D
R
6
A6 A5
A3
A4
A2 A1 1
D
w
6 D
w
5
D
w
7
Timing Diagram of Short Addressing Mode
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