Hioki SM7810, Instruction Manual

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4.5 Communication Methods
28
Status Byte Register (STB) ______________________________________
A status byte register is an 8-bit register output from the unit to the controller dur-
ing serial polling. If even one of the status byte register bits enabled by the ser-
vice request enable register changes from "0" to "1" the MSS bit becomes 1. At
the same time, the RQS bit also becomes "1" and a service request is gener-
ated.
The RQS bit is always synchronized with the service request and only read and
simultaneously cleared upon being serial polled. The MSS bit is only read by an
"
*
STB? " query and is not cleared until the event is cleared by a command such
as a "
*
CLS
" command.
Service Request Enable Register (SRER) __________________________
This register masks the Status Byte Register. Setting a bit of this register to 1
enables the corresponding bit of the Status Byte Register to be used.
Bit 7 ERR
Unrecoverable error
Bit 6 RQS
Set to 1 when a service request is dispatched.
MSS
This is the logical sum of the other bits of the Status Byte Regis-
ter.
Bit 5 ESB Standard Event Status (logical sum) bit
This is logical sum of the Standard Event Status Register.
Bit 4 MAV
Message available
Indicates that a message is present in the output queue.
Bit 3 DSB Event Status (logical sum) bit
This is the logical sum of Event Status Register.
Bit 2
− unused
Bit 1
− unused
Bit 0
− unused