Hioki SM7810, Instruction Manual

Page: 33 / 69

4.5 Communication Methods
30
Standard Event Status Enable Register (SESER) ____________________
Setting any bit of the Standard Event Status Enable Register to 1 enables
access to the corresponding bit of the Standard Event Status Register.
Standard Event Status Register (SESR) and Standard Event Status Enable
Register (SESER)
Device Event Status Registers (DESR)_____________________________
This instrument provides specific event status registers for controlling events.
Each event register is an 8-bit register.
When any bit in one of these event status registers enabled by its corresponding
event status enable register is set to 1, bit (DSB) of the Status Byte Register is
set to 1.
Device Event Status Registers are cleared in the following situations:
• When a "
* CLS
" command is executed
• When an Event Status Register query ( DSR? ) is executed
• When the instrument is powered on
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PON URQ CME EXE DDE QYE RQC OPC
& & & & & & & &
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PON URQ CME EXE DDE QYE RQC OPC
Standard Event Status Register (SESR)
Standard Event Status Enable Register (SESER)
bit 6 bit 5 bit 4
SRQ
MSS
ESB MAV
Logical
sum
Bit 7
−
Unused
Bit 6
−
Unused
Bit 5 BOV Reserved bit
Bit 4 BFL Reserved bit
Bit 3 STP Measured stop event
Bit 2 ITL Reserved bit
Bit 1 LM2 Reserved bit
Bit 0 LM1 Reserved bit