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HAMEG Instruments GmbH • Industriestr. 6 • D-63533 Mainhausen • Deutschland
Subject to change without notice
Tel.: +49 (0) 6182 800 0 • Fax: +49 (0) 6182 800 100 • E-Mail: [email protected]
Geschäftsführer: Dipl.-Ing. Holger Asmussen, Dipl.-Ing. Andre Vander Stichelen • AG Offenbach am Main HRB 41200
1
1
HAMEG Instruments GmbH • Industriestraße 6 • D-63533 Mainhausen
Subject to change without notice
Tel.: +49 (0) 6182 800 0 • Fax: +49 (0) 6182 800 100 • E-Mail: [email protected]
Geschäftsführer: Dipl.-Ing. Holger Asmussen • AG Offenbach am Main HRB 41200
Firmware Version: 01.020 and later
English
S C P I P r o g r a m m e r s M a n u a l
H M S S e r i e s
1
HAMEG Instruments GmbH • Industriestraße 6 • D-63533 Mainhausen
Subject to change without notice
Tel.: +49 (0) 6182 800 0 • Fax: +49 (0) 6182 800 100 • E-Mail: [email protected]
Geschäftsführer: Dipl.-Ing. Holger Asmussen • AG Offenbach am Main HRB 41200
Firmware Version: 01.020 and later
English
S C P I P r o g r a m m e r s M a n u a l
H M S S e r i e s
HMO352x, HMO2524
HMO72x ... HMO202x
Firmware Version: 03.00 and later
English
:ACQuire
:CHAN1OFFSet
:DISPlay
:HCOPy
*ESR?
*OPC?
:LOGic:SIZE
:MEASure
:POD1
:SYSTem
S C P I P r o g r a m m e r s M a n u a l
H M O S e r i e s
SCPI Commands HMC8012
Bit No. Meaning
0...1
Not used
2
Error Queue
The bit is set when an error is occured. If this bit is enabled by the SRE, each entry of the error
queue generates a service request. Thus an error can be recognized and specified in greater detail
by polling the error queue. The poll provides an informative error message. This procedure is to be
recommended since it considerably reduces the problems involved with remote control.
3
QUEStionable status sum bit
The bit is set, if an
EVENt
bit is set in the
QUEStionable
status register and the associated
ENABle
bit is set to 1. A set bit indicates a questionable instrument status, which can be specified in detail
by polling the
QUEStionable
status register.
4
MAV bit (message available)
The bit is set, if a readable message in the output buffer is available. This bit can be used to enable
data to be automatical read from the instrument.
5
ESB bit
Sum bit of the event status register. It is set, if one of the bits in the event status register is set and
enabled in the event status enable register. Setting of this bit indicates a serious error, which can be
specified in greater detail by polling the event status register.
6
MSS bit (master status summary bit)
The bit is set, if the instrument triggers a service request. This is the case, if one of the other bits of
this register is set together with its mask bit in the service request enable register SRE.
7
OPERation
status register sum bit
The bit is set, if an
EVENt
bit is set in the
OPERation
status register and the associated
ENABle
bit
is set to 1. A set bit indicates that the instrument is just performing an action. The type of action can
be determined by polling the
OPERation
status register.
Table 1.8: Bits of the status byte
(please refer to page 20)
Event Status Register (ESR) and Event Status Enable Register (ESE)
The ESR is defined in IEEE 488.2. It can be compared with the
EVENt
part of a SCPI register. The event status register
The ESE corresponds to the
ENABle
part of a SCPI register. If a bit is set in the ESE and the associated bit in the ESR
changes from 0 to 1, the ESB bit in the STB is set. The ESE register can be set using the command
and read
using the command
*ESE?
.