6 Configuration Mode Introduction
6.2 JTAG Configuration
UG290-2.5.2E
46(98)
After one Y-page is written in each time, GW1N(Z)-2/4/6/9 needs to
perform Run-Test for 13-15 μs; GW1N(S)-2(C) needs to perform Run-Test
for 30-35 μs. No extra clock is required for the other series of devices.
Note!
If you want to read data from Configuration Data, high 4 Bytes will be taken. If you want to
write data into Shift-DR, LSB will begin to write.
Figure 6-21 Y-page Programming
Start
End
Run-Test 13
μS(GW1N(Z)-
2/4/6/9)
Or
Run-Test 30
μS(GW1NS(E)-
2(C))
Move TAP to SHIFT-DR
Transfer 4 Bytes (LSB
)
Move Tap to Exit-DR,
Update-DR&Run-Test-Idle
Process of Reading internal Flash
This chapter introduces the process of reading internal Flash briefly,
no rate requirements for the TCK of JTAG, as shown in Figure 6-22.
Reading the internal Flash can be regarded as the reverse process of
programming Flash. But firstly, you should make sure that the written-in
Readable-pattern has taken effect. For GW1N, the Reprogram(0x3C) and
Noop(0x02) can be sent in turn after Readable-pattern is written-in to make
the internal flash be Readable.
Process Description:
1.
Check ID Code. (optional);
2.
Send the "0x15" instruction of ConfigEnable;
3.
Send EF-Read instruction 0x73;
4.
Send read Flash start address 0x0. The method is same as write
