6 Configuration Mode Introduction
6.4 SSPI
UG290-2.5.2E
61(98)
The timing of 0x1500 and 0x3A is basically the same. Instructions start
at CS low level and the CS is pulled up after the instruction transmission is
completed. Instructions following this timing are as follows: 0x3C00
(Reconfig / Reprogram), 0x1500(Write Enable), 0x3A000 (Write Disable),
0x1600(Program SPI Flash), 0x1200(Init Address), 0x0500(Erase SRAM).
In addition, SSPI is driven by an external clock, so if CS is at high
before and after these instructions, more than two clocks are needed to
enable FPGA to collect the state of CS.
Write Data (0x3B)
The fs file is sent directly to the FPGA device using the ”Write Data
(0x3B)” instruction.
Note that CS keeps low level in the process of data writing.
Figure 6-36 Write Data (0x3B) Timing