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4 Configuration Process

4.1 Power-up Sequence

UG290-2.5.2E

10(98)

4.1

Power-up Sequence

During the power-on process, the power-on reset (POR) circuit inside

the FPGA becomes active. The actie POR circuit makes sure the external
I/O pins are in a high-impedance state and monitors the
VCC/VCCX/VCCOn input rails. When VCC/VCCX/VCCOn meets the
minimum reset voltage level (Voltage level may vary for different devices,
and different devices monitor different power rails.), POR circuit releases
an internal reset signal, allowing the FPGA to bigin its initialization process.
When READY and DONE are driven low, the FPGA moves to the
initialization state, as shown in Figure 5-2.

Figure 4-1 POR Power-up Timing

tINTL

VCC/VCCX/VCCOn

READY

DONE

Table 4-1 lists different power rails monitored by POR circuits of

different devices.

Table 4-1 Power Rails Monitored by POR Circuits of Different Devices

Series

Device

Power Rails

GW1N

GW1N-1
GW1N-4
GW1N-9

VCC/VCCX/VCCO1/VCCO3

GW1N-1P5
GW1N-2

VCC/VCCX/VCCO0

GW1N-1S

VCC/VCCX/VCCO0/VCCO2

GW1NZ

GW1NZ-1

VCC/VCCX/VCCO1/VCCO3

GW1NR

GW1NR-1
GW1NR-4
GW1NR-9

VCC/VCCX/VCCO1/VCCO3

GW1NS

GW1NS-4
GW1NS-4C

VCC/VCCX/VCCO0/VCCO1

GW1NSR

GW1NSR-4
GW1NSR-4C

VCC/VCCX/VCCO0/VCCO1

GW1NSE

GW1NSE-4C

VCC/VCCX/VCCO0/VCCO1

GW1NSER

GW1NSER-4C

VCC/VCCX/VCCO0/VCCO1

GW1NRF

GW1NRF-4B

VCC/VCCX/VCCO1/VCCO3

GW2A

GW2A-18
GW2A-55

VCC/VCCX/VCCO3

GW2AR

GW2AR-18

VCC/VCCX/VCCO3

GW2AN

GW2AN-9X

VCC/VCCX/VCCO1/VCCO5

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Summary of Contents for GW2AR Series

Page 1: ...Gowin FPGA Products Programming and Configuration Guide UG290 2 5 2E 07 14 2022 ...

Page 2: ...ronic mechanical photocopying recording or otherwise without the prior written consent of GOWINSEMI Disclaimer GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Condit...

Page 3: ...ts deleted 8 16 2019 1 06E Power up description and configuration flow added The description of File Size Configuration modified 5 15 2020 2 0E The note of JTAGSEL_N used as IO added GW1N R 2 GW1N R 2B GW1N R 6 removed Configuration mode description optimized 8 20 2020 2 1E JTAG Configuration added SSPI Configuration added AES Programming added 10 30 2020 2 2E Configuration File Loading Time added...

Page 4: ...4 1 Power up Sequence 10 4 2 Initialization 11 4 3 Configuration 11 4 4 Wake up 11 4 5 User Mode 12 5 Configuration Pin 13 5 1 Configuration Pin List and Reuse Options 13 5 1 1 Configuration Pin List 13 5 1 2 Configuration Pin Reuse 14 5 2 Configuration Pin Function and Application 16 6 Configuration Mode Introduction 21 6 1 Configuration Notes 21 6 2 JTAG Configuration 25 6 2 1 JTAG Configuration...

Page 5: ...67 6 5 5 MSPI Configuration Timing 71 6 6 DUAL BOOT Configuration Supported by LittleBee Family Only 72 6 7 CPU Mode 74 6 7 1 Configuration Timing 75 6 8 SERIAL Mode 75 6 9 I2 C Mode 77 6 9 1 Process of GW1N 2 Configuring or Programming SRAM Flash 80 7 Bitstream File Configuration 81 7 1 Configuration Options 81 7 2 Configuration Data Encryption Supported by Arora Family only 82 7 2 1 Definition 8...

Page 6: ...2 Read ID Code Data Register Access Timing 31 Figure 6 13 SRAM Configuration Flow 33 Figure 6 14 Process of reading SRAM 35 Figure 6 15 Process of Normal Programming 37 Figure 6 16 Process of Background Programming 38 Figure 6 17 The Embedded Flash Erasing process of T Technology 40 Figure 6 18 The Embedded Flash Erasing process of H Technology 42 Figure 6 19 Process of Programming Internal Flash ...

Page 7: ...tribution in Flash Memory 68 Figure 6 45 Input the Start address for the Next Bitstream 69 Figure 6 46 Set the Programming Address for the External Flash 70 Figure 6 47 Connection Diagram for Configuring Multiple FPGAs via Single Flash 71 Figure 6 48 MSPI Download Timing 71 Figure 6 49 Multiple FPGA Connection Diagram in MSPI Configuration Mode 72 Figure 6 50 Dual Boot Flow Chart 73 Figure 6 51 Co...

Page 8: ...The Process of Sending Instructions 30 Table 6 7 Count of Address and Length of One Address 34 Table 6 8 TCK Frequency Requirements for JTAG 38 Table 6 9 Readback pattern Autoboot pattern 43 Table 6 10 Pin State 52 Table 6 11 Status Register Definition 54 Table 6 12 SSPI Mode Pins 57 Table 6 13 SSPI Configuration Timing Parameters 58 Table 6 14 Configuration Instruction 59 Table 6 15 Pin Descripti...

Page 9: ...List of Tables UG290 2 5 2E vi Table 7 4 Loading Time in Autoboot Mode 93 Table 10 1 SPI Flash Operation Instruction 98 ...

Page 10: ...Products Data Sheet DS226 GW2AR series of FPGA Products Data Sheet DS961 GW2ANR series of FPGA Products Data Sheet DS821 GW1NS series of FPGA Products Data Sheet DS841 GW1NZ series of FPGA Products Data Sheet DS861 GW1NSR series of FPGA Products Data Sheet DS871 GW1NSE series of FPGA Products Data Sheet DS881 GW1NSER series of FPGA Products Data Sheet DS891 GW1NRF series of FPGA Products Data Shee...

Page 11: ...ream Bitstream Data Configuration Mode Configuration Mode EFlash EmbFlash Embedded Flash Internal Flash Internal Flash Programming Programming Edit Mode Edit Mode User Mode User Mode Background Programming Embedded Flash Background Programming LSB Least Significant Bit MSB Most Significant Bit TAP Test Access Port Security Bit Security Bit Bscan Boundary Scan I2C I2C IIC Inter Integrated Circuits ...

Page 12: ...vice supports depend on the device model and package MODE 2 0 A representation of the three MODE pin values associated with GowinCONFIG AUTO BOOT Configuration FPGA loads bitstream data into the SRAM from an embedded Flash Only non volatile devices support this mode DUAL BOOT Configuration Two bitstream files are stored in embedded Flash and external Flash separately Switch to the embedded Flash i...

Page 13: ...d data can only be transmitted between adjacent devices User Mode Hands over control to users when the FPGA configuration has been completed Only in user mode configuration pins can be reused as GPIOs Gowin Programmable I O Edit Mode FPGA can be programmed and configured in this mode All configuration pins cannot be reused as GPIOs The output of all GPIOs is high impedance state except transparent...

Page 14: ...at is commonly used in the industry the LittleBee Family of FPGA products also support GOWINSEMI s own configuration mode GowinCONFIG GowinCONFIG configuration modes that are available and supported for each device depend on the device model and package All non volatile devices support JTAG and AUTO BOOT modes Up to six configuration modes are supported as shown in Table 3 1 ...

Page 15: ...ily via DIN interface CPU 5 111 External Host configure FPGA products of LittleBee Family via DBUS interface Note 1 The unbound mode pins are grounded by default 2 The JTAG configuration mode is independent of MODE value 3 The SPI interfaces of the SSPI and MSPI modes are independent of each other 4 Currently GW1N R 4 GW1N R 4B do not support DUAL BOOT 5 The CPU configuration mode and SERIAL confi...

Page 16: ...ation Modes MODE 2 0 1 Description JTAG XXX2 External Host configures Arora Family of FPGA products via JTAG interface GowinCONFIG MSPI 000 As Master FPGA reads data from external Flash or other devices via the SPI interface3 SSPI 001 External Host configures Arora Family of FPGA products via SPI interface SERIAL4 101 External Host configures Arora Family of FPGA products via DIN interface CPU4 11...

Page 17: ...ation Process UG290 2 5 2E 8 98 4Configuration Process After power on the FPGA goes through a sequence of states including initialization SRAM configuration and wake up The configuration flow is as shown in below ...

Page 18: ... Driven Low Initialization READY Driven High and MODE Value Sampled Write SRAM Memory and Verify FPGA Waken Up DONE Driven High User Mode RECONFIG_N or READY Low RECONFIG_N High READY Low ERROR All configuration data received RECONFIG_N Driven Low or Device Refresh RECONFIG_N Driven Low or Device Refresh RECONFIG_N Driven Low or Device Refresh ...

Page 19: ...GA moves to the initialization state as shown in Figure 5 2 Figure 4 1 POR Power up Timing tINTL VCC VCCX VCCOn READY DONE Table 4 1 lists different power rails monitored by POR circuits of different devices Table 4 1 Power Rails Monitored by POR Circuits of Different Devices Series Device Power Rails GW1N GW1N 1 GW1N 4 GW1N 9 VCC VCCX VCCO1 VCCO3 GW1N 1P5 GW1N 2 VCC VCCX VCCO0 GW1N 1S VCC VCCX VC...

Page 20: ...d via multiple modes according to the MODE pin values During the time the FPGA receives its configuration data the READY pin can indicate its internal state When READY is high configuration proceeds without issue If READY is low an error has occurred and the FPGA does not operate 4 4 Wake up When all the configuration data is reveived correctly the FPGA enters the wake up state and set the interna...

Page 21: ...ations you designed immediately The FPGA will remains in this state until one of the following three events occurs The RECONFIG_N pin is externally driven low A REFRESH command is received via one of the configuration ports Power is cycled Once one of the three envents above occurs the FPGA will enter the configuration process again ...

Page 22: ...s and also can be reused as GPIO Users can configure the pins as required Users also can configure them according to their configuration functions to meet specific requirements 5 1 Configuration Pin List and Reuse Options 5 1 1 Configuration Pin List Table 5 1 contains a list of all the configuration pins of Gowin FPGA products together with the details of the pins used in each configuration mode ...

Page 23: ...o maximize the utilization of I O Gowin FPGA products support setting the configuration pins as GPIO pins Before any configuration operation is performed on all series of Gowin FPGA products after power up all related configuration pins are used as configuration pins by default After successful configuration the device enters into user mode and reassigns the pin functions according to the multiple...

Page 24: ... Dedicated configuration pins Set as GPIO Used as GPIO after configuration DONE Default Status Dedicated configuration pins Set as GPIO Used as GPIO after configuration Note 1 For the devices with JTAGSEL_N unbound when debugging JTAG pin reuse it s suggested to set MODE value to non auto configuration mode being neither auto boot dual boot nor MSPI before power up to avoid the other bit stream da...

Page 25: ...function for the FPGA programming configuration FPGA can t be configured if RECONFIG_N is set to low Keep high level during FPGA powering up until the powering up is stable for 1ms As a configuration pin a low level signal with pulse width no less than 25ns is required for GowinCONFIG to reload bitstream data according to the MODE setting value You can also write logic to control the pin to trigge...

Page 26: ...ng Otherwise the FPGA will fail to enter the user mode after being configured MODE GowinCONFIG modes selection pin As the selection pin of GowinCONFIG modes MODE is an input pin that has internal weak pull up The maximum bit width is 3 bits When FPGA powers up or a low level pulse triggers RECONFIG_N the device enters the corresponding GowinCONFIG mode in accordance with the MODE value The same MO...

Page 27: ...ype TDO As a configuration pin it is an output pin It is a serial data output pin in JTAG configuration mode As a GPIO it can be used as an input or output type SCLK As a configuration pin it is an input pin It is a clock input pin in SSPI SERIAL and CPU configuration modes As a GPIO it can be used as an input or output type CLKHOLD_N As a configuration pin it is an input pin with internal weak pu...

Page 28: ...y Setting MCS_N As a configuration pin it is an output pin It is a chip selection signal in MSPI configuration mode active low As a GPIO it can be used as an input or output type MI As a configuration pin it is an input pin It is a serial data input pin in MSPI configuration mode As a GPIO it can be used as an input or output type MO As a configuration pin it is an output pin Serial data output pi...

Page 29: ...ull up It is a serial data input pin in the SERIAL configuration mode As a GPIO it can be used as an input or output type DOUT As a configuration pin it is an output pin It is a serial data output pin in the SERIAL configuration mode which is only used as the input to the latter device when the FPGA is cascading As a GPIO it can be used as an input or output type SCL As a configuration pin it is a...

Page 30: ...T or DUAL BOOT configuration The mode value for each configuration is different 6 1 Configuration Notes GOWINSEMI FPGA products include LittleBee family and Arora family Whether the name of the device contains R does not affect the configuration feature the main difference is that SDRAM PSRAM is integrated in all FPGA products that have a serial number that includes the letter R Except DUALBOOT co...

Page 31: ...sh can only be programmed via the JTAG interface and the clock rate is no less than 1MHz Please refer to Table 6 8 for the clock rate Note During configuring SRAM devices via built in Flash AUTOBOOT configuration and DUALBOOT configuration and programming built in Flash the FPGA needs to remain powered up and the RECONFIG_N cannot be triggered at low level otherwise it may cause irreparable damage...

Page 32: ... Figure 6 1 Figure 6 1 Recommended Pin Connection FPGA MODE 0 MODE 1 MODE 2 RECONFIG_N READY DONE 4 7K LED DC3 3V 4 7K DC3 3V LED 4 7K DC3 3V 1K 1K KEY 1K Note Add the dial switch to change the MODE value Some MODE pins of devices are not all bonded out and the unbonded MODE pins are grounded by default The values of READY and DONE signals have no meaningful reference in JTAG configuration The unb...

Page 33: ...d RECONFIG_N Trigger Name Description Min Max Tportready 1 Time from application of VCC VCCX and VCCO to the rising edge of READY 50μs 200μs Trecfglw RECONFIG_N low pulse width 25ns Trecfgtrdyn Time from RECONFIG_N falling edge to READY low 70ns Treadylw READY low pulse width TBD Trecfgtdonel Time from RECONFIG_N falling edge to READY low 80ns Note In the case of MODE0 0 the device power up waitin...

Page 34: ...figuration data is lost after the device is powered down All Gowin FPGA products support the JTAG configuration mode 6 2 1 JTAG Configuration Mode Pins The relevant pins for the JTAG configuration mode are shown in Table 6 3 Table 6 3 Pin Description in JTAG Configuration Mode Pin Name I O Description JTAGSEL_N1 I internal weak pull up Revert JTAG pin from GPIO to configuration pin Low active TCK ...

Page 35: ... and JTAG pin will be used as a GPIO The clock frequency for JTAG configuration mode is no higher than 40MHz In addition to using JTAG to configure SRAM the built in Flash of Gowin non volatile FPGA devices LittleBee Family and the external SPI Flash of all other FPGA series programming can also be configured through the JTAG pin The connection for programming the built in Flash of the non volatil...

Page 36: ...n be connected or not as appropriate 6 2 3 JTAG Configuration Timing See Figure 6 6 for the timing of JTAG mode Figure 6 6 JTAG Configuration timing See Table 6 4 for the description of timing parameters Table 6 4 JTAG Configuration Timing Parameters Name Description Min Max Ttckftco Time from TCK falling edge to output 10ns Ttckftcx Time from SCLK falling edge to high impedance 10ns Ttckp TCK clo...

Page 37: ...h logic 1 and at least 5 strobes are input higher and then low at the TCK terminal the TAP logic is reset the TAP state machine in other states is converted into the state of test logic reset and the JTAG port and the test logic are reset Note The CPU and peripherals are not reset in this state Note The data on the TDO is valid from the falling edge of TCK in the Shift_DR or Shift_IR state The dat...

Page 38: ...nt to the DR in the Shift_DR state as shown in Figure 6 9 The data is sent in LSB way or MSB way depending on specific operations Figure 6 8 Instruction Register Access Timing Figure 6 9 Data Register Access Timing Note The total length of the instruction register is 8 bits in the GW1N R and GW2A R series of the FPGA The length of the data register can vary depending on the selected register Read ...

Page 39: ...least 5 clock cycles are continuously transmitted 2 Move the state machine from Test Logic Reset to Run Test Idle 3 Move the state machine to Shift IR Send Read ID instruction 0x11 beginning with LSB When MSB the last bit is being sent move state machine to Exit1 IR at the same time i e TMS should be high level before sending MSB Table 6 6 shows the change of TDI and TMS value during sending 0x11 ...

Page 40: ...0 Read Machine Flow Chart in ID Code State Start Move TAP to Shift IR Transfer Read ID Code 0x11 instruction LSB Move TAP to Exit1 IR End Move TAP to Update IR Move TAP to Run Test Idle Move TAP to Shift DR Transfer 32 clocks to get ID Code Move TAP to Exit1DR Move TAP to Update DR Move TAP to Run Test Idle Figure 6 11 The Access Timing of Read ID Code Instruction 0x11 Figure 6 12 Read ID Code Dat...

Page 41: ...d the device ID CODE and check if it matches 3 Erase the SRAM if it has been configured Please refer to SRAM Erasure Process 4 Send the 0x15 instruction of ConfigEnable 5 Send the 0x12 instruction of Address Initialize 6 Send the 0x17 instruction of Transfer Configuration Data 7 Move the state machine to Shift DR Data Register Send Configuration Data from the MSB bit by bit till all the bitstream ...

Page 42: ...2 See Read Flow Transfer Config Enable Instruction 0x15 Transfer Address Init Instruction 0x12 N Y SRAM Erase Option Process of Reading SRAM Warning SRAM data is not allowed to be read back by default Read the SRAM data from the SRAM area of the FPGA First ensure that the security bit is not configured when the data are written to the SRAM The security bit is used to protect the runtime data and e...

Page 43: ...ding process is described in detail below as shown in Figure 6 14 1 Send the 0x15 instruction of ConfigEnable 2 Send the 0x12 instruction of Address Initialize 3 Send the 0x 03 instruction of SRAM Read 4 Move the state machine to Shift DR data register and send as many clocks as the value of the address length see Table 6 7 When the last clock is sent pull up TMS at the same time The state machine...

Page 44: ...ute the checksum 16bit Transfer Config Disable Instruction 0x3A Transfer Config Enable Instruction 0x15 Process of Erasuring SRAM When reconfiguring SRAM the existing SRAM needs to be erased The flow is as follows 1 Send the 0x15 instruction of ConfigEnable 2 Send the 0x05 instruction of SRAM Erase 3 Send the 0x02 instruction of Noop 4 Delay or Run Test 2 10ms 5 Send the 0x09 instruction of SRAM E...

Page 45: ...ng after the instructions of EraseSram 0x05 and Noop 0x02 are sent The reference time for GW1N 1 is 1ms The reference time for GW1N 4 is 2ms The reference time for GW1N 9 is 4ms The reference time for GW2A 18 is 6ms The reference time for GW2A 55 is 10ms Process of Programming Internal Flash Programming the internal flash includes normal programming and background programming Show the programming ...

Page 46: ... Normal Programming Start Verify ID Code Read Status Erase SRAM Erase Flash Program Flash DoneFinal 1 DoneFinal 0 Read Status DoneFinal 0 Send Reconfig Instruction 0x3C And Sleep 10ms DoneFinal 1 Stop If need to read back to verify data Please use Readable pattern at the 1st Y page of the 1st X page ...

Page 47: ...requirements for JTAG programming frequency are different according to the different processes of the GW1N series of the embedded Flash Please refer to Table 6 8 Table 6 8 TCK Frequency Requirements for JTAG Device TCK Frequency Range Process Code GW1N 1 GW1N 1S 1 4MHz 5MHz H GW1N RF 4B GW1N SER 4C GW1N R 9 C GW1NZ 1 1MHz 5MHz T GW1NS E 2 C 1MHz 5MHz S FPGA erasure process of T Technology The foll...

Page 48: ...Shift DR Transfer 32 bits Exit1 DR Update DR Run Test ldle This step only applied to GW1N 4 Skip this step for other devices 8 The clock Run Test is continuously generated in Run Test Idle for 120ms Please refer to Table 6 8 for the frequency requirements 9 Send the 0x3A instruction of Config Disable 10 Send the 0x02 instruction of Noop to end the erasure process 11 Send the 0x03 instruction of Re...

Page 49: ... ms Transfer Config Disable Instruction 0x3A Transfer Read ID Code Instruction 0x11 Transfer Repogram Instruction 0x3C Transfer Noop Instruction 0x02 Note Ignore the shading area operation during Background Programming FPGA erasure process of H Technology FPGA erasure process of H Technology 1 Send the 0x15 instruction of ConfigEnable 2 Send the 0x75 instruction of EFlash Erase 3 Move the state ma...

Page 50: ... all 5 The clock Run Test is continuously generated in Run Test Idle for 120ms Please refer to Table 6 8 for the frequency requirements 6 Send the 0x3A instruction of Config Disable 7 Send the 0x03 instruction of Reprogram to check if the erasing is successful 8 Send the 0x02 instruction of Noop to end the erasure process ...

Page 51: ...ansfer SRAM Erase Instruction 0x05 Transfer SRAM Erase Done Instruction 0x09 Transfer EFlash Erase Instruction 0x75 Run Test 96 ms Transfer Config Disable Instruction 0x3A Transfer Noop Instruction 0x02 Run Test 1ms GW1NS E 2 C Erasure Process of S Technology GW1NS E 2 C offers two built in Flash Note the different Flash when programming Refer to the process below 1 Check if the device ID is match...

Page 52: ...evices with the feature of background programming just need to use Autoboot pattern Autoboot pattern data must be inserted in the header of bitstream file in the case of no requirements of reading back data If an X page is less than 256Bytes you can use 0xFF or 0x00 to complement it The requirements for JTAG programming frequency are different according to the different processes of the embedded F...

Page 53: ...rify See Read EFlash Flow End Y N Transfer Noop Instruction 0x02 See ReadIDCode Same as FS file Y N Erase Flash Verify Y Program the first X page with readable pattem Erase Flash Transfer Reprogram Instruction 0 x 3C N Program Bitstream to pages one page have 64 X pages one X page have 4Y pages Process of Programming an X page The process of programming an X page is as shown in Figure 6 20 1 Send ...

Page 54: ...1 0x13 the written in address is 00000000000000000000010011000000 The address data is written in LSB way Jump out of Shift DR at the last bit Figure 6 20 X page Programming Start End Delay 16000ns Program 1 X Page Transfer Config Enable Instuction 0x15 Transfer EF Program Instuction 0x71 Address index 0 Y Delay 16000ns in Run Test Idle Transfer address data LSB N Delay 6μS GW1N Z 2 4 6 9 Or 2400μS...

Page 55: ...HIFT DR Transfer 4 Bytes LSB Move Tap to Exit DR Update DR Run Test Idle Process of Reading internal Flash This chapter introduces the process of reading internal Flash briefly no rate requirements for the TCK of JTAG as shown in Figure 6 22 Reading the internal Flash can be regarded as the reverse process of programming Flash But firstly you should make sure that the written in Readable pattern h...

Page 56: ...to end the process Figure 6 22 Process of Reading Internal Flash Start Check ID Code See ReadIDCode Transfer Config Enable Instruction 0x15 Y N Y Transfer EF Read Instruction 0x73 Transfer address 0x0 data LSB Transfer Config Disable Instruction 0x3A End Read pages N Process of Reading a Page Y page Flash Reading a Y page is similar to writing a Y page but there is no waiting time for writing in F...

Page 57: ... data from TDO data is LSB End Move TAP to Exit1 DR Update DR Run Test Idle Background Programming The device sometimes needs to upgrade the data file and program the Flash without affecting current functions And it can maintain the I O state when adding a new data stream file The following is the flow of GW1N4 that upgrades the internal Flash data using the Background Programming ...

Page 58: ...uration UG290 2 5 2E 49 98 Figure 6 24 GW1N 4 Background Programming Flow Start Flash Erase Flash Program Verify Flash Readback Toggle reconfig_N pin Transfer JTAG Instructions Sample 0x01 Extest 0x04 End N NG Y Y Transfer JTAG Instructions NOOP 0xFF ...

Page 59: ...Shift IR Transfer Sample Instruction 0x01 Update IR Select DR Scan Exit1 DR Update DR Select DR Scan Shift IR Transfer Extest Instruction 0x04 Run TEST IDLE Update IR Capture DR End Note 1 Jump directly from Update IR to Select DR Scan ExFlash Programming Gowin FPGA can load bitstream files from external Flash and program external Flash through JTAG directly ...

Page 60: ...m of programming external Flash via JTAG Program External Flash via JTAG SPI In this mode the external Flash can be programed via JTAG The principle of this mode is to convert JTAG protocol to SPI protocol and then program external Flash Users program SPI Flash by simulating Master SPI timing through JTAG Figure 6 27 Process View of Programming SPI Flash SPI Start Check ID Code See RaadIDCode Prog...

Page 61: ...iple of this mode is changing the state of the pins connected to SPI by using Boundary Scan method to implement SSPI timing and then to program the internal Flash The length of the Boundary Scan Chain used in this mode is 8 bits Every two bits combination corresponds to the pin state as shown in Table 6 10 One SCLK drive is completed every two times of sending Boundary Scan Chain Table 6 10 Pin St...

Page 62: ... means input data 0 means low 1 means high Figure 6 30 Process of Use Boundary Scan Mode To Program SPI Flash Start Check ID Code See RaadIDCode Transfer BSCAN_2_SPI Instruction 0x3D Program or read SPI through JTAG End Y N Transfer Config Disable Instruction 0x3A Transfer Config Enable Instruction 0x15 ...

Page 63: ...s the read instruction is 0x41 and the timing is the same as that of Read ID Code The meaning of the Status Register is shown in Table 6 11 Table 6 11 Status Register Definition Device Status Register 31 0 GW1N R 1 2 4 GW1NS 2 GW1NS R 2C GW1N R 6 9 GW1NZ 1 GW2A 18 55 0 CRC Error 1 Bad Command Error 2 ID Verify Failed Error 3 Timeout Error 4 0 5 6 7 8 9 0 10 11 12 Gowin VLD 1 0 13 Done Final 14 Sec...

Page 64: ...iagram of Daisy Chain Figure 6 31 Connection Diagram of Daisy Chain Routine File For the routine file please contact GOWINSEMI technical support or the local office 6 3 AUTO BOOT Configuration Supported by LittleBee Family Only The AUTO BOOT mode is a configuration mode for momentary connection feature of non volatile LittleBee family of FPGA Products The Arora Family of FPGA products do not suppo...

Page 65: ...gure the SRAM to complete AUTO BOOT after the built in Flash is programmed using Gowin programmer The momentary connection feature of the built in Flash saves download time and improves productivity GW1N R 9 and GW1NS series support two retries of AUTO BOOT configuration i e the devices can be automatically reconfigured if the first configuration fails after power up The other devices of LittleBee...

Page 66: ...ed and configured Low level Programming configuration for FPGA is prohibited DONE I O High level pulse Successfully programmed and configured Low level pulse Programming and configuration uncompleted or failed MODE 2 0 I Internal weak pull up Configuration mode selection READY rising edge sampling SCLK I Input clock CLKHOLD_N I Internal weak pull up High level SPI operation corresponding to SCLK i...

Page 67: ...dge to high impedance 10ns Tcsnhw CSN high time 25ns Treadytcsl Time from READY rising edge to CSN low 10μs Treadytsclk Time from READY rising edge to first SCLK edge 10μs Other than the power requirements the following conditions need to be met to use the SSPI configuration mode SSPI port enable RECONFIG_N is not set as a GPIO during the first configuration after power up or the previous programm...

Page 68: ... Erase SRAM 0x0500 Read ID Code The length of FPGA ID Code is 32bits The instruction to read ID is four bytes that is 0x11000000 Before sending instructions keep CS at a high level and generate multiple clocks more than two to let FPGA get CS state After CS is pulled down the instruction of 0x11000000 is written in in MSB way and after this 32 clocks are generated continuously At this time the ID ...

Page 69: ...evel more than two clocks should be given to SCLK to drive FPGA to identify CS signal This rule also applies to other instructions Write Disable 0x3A00 After finishing sending data exit programming mode using Write Disable After exiting the device can be awakened to enter the working state Figure 6 35 Write Disable 0x3A00 Timing ...

Page 70: ...Reprogram 0x1500 Write Enable 0x3A000 Write Disable 0x1600 Program SPI Flash 0x1200 Init Address 0x0500 Erase SRAM In addition SSPI is driven by an external clock so if CS is at high before and after these instructions more than two clocks are needed to enable FPGA to collect the state of CS Write Data 0x3B The fs file is sent directly to the FPGA device using the Write Data 0x3B instruction Note ...

Page 71: ...win programmer The connection diagram for programming an external Flash via SSPI is shown in Figure 6 38 Figure 6 38 Connection Diagram of Programming External Flash via SSPI FPGA CLKHOLD_N SCLK MCLK SSPI_CS_N MCS_N SI MI SO MO Host CTRL CLK CS_N DOUT DIN Flash CLK CS_N DOUT DIN Note All Arora family devices support programming external Flash via SSPI For the LittleBee family devices currently onl...

Page 72: ... Flow of Programming External Flash via SSPI Start Transfer Program SPI Flash Instruction 0x1600 Program Flash following SPI timing End 6 4 5 Multiple FPGA Connection View in SSPI Mode Figure 6 40 Multiple FPGA Connection Diagram 1 Figure 6 41 Multiple FPGA Connection Diagram 2 ...

Page 73: ...stream from external Flash either Power Cycle the FPGA Or pulse RECONFIG_N low MSPI Mode External Flash Update The external Flash memory can also be re programmed via the FPGA using JTAG This feature enables the FPGA to support bitstream back ground updates and is often referred to as infield or remote update Once the FPGA has been configured users can remotely write new configuration data to the ...

Page 74: ...d 1 b0 Programming and configuration incomplete MODE 2 0 I Internal weak pull up MODE select sampled on rising edge of READY MCLK O SPI output clock MCS_N O SPI chip select active low MO O SPI output data to Slave MI I SPI Input Data from Slave FASTRD_N I Sampled on rising edge of READY 1 b1 Read SPI mode SPI instruction 0x03 1 b0 Fast Read SPI mode SPI instruction 0x0B Note The MSPI configuration...

Page 75: ...R The other fixed pins are shown in Figure 6 1 The FASTRD_N pin can remain floating in MSPI mode if the clock frequency is less than 30 MHz External Flash programming via the FPGA using JTAG is shown in Figure 6 43 The connection diagram for programming external Flash via the SSPI interface is shown in Figure 6 38 Figure 6 43 Connection Diagram of JTAG Programming External Flash FPGA TDI MCLK TCK ...

Page 76: ...OOT MULTIBOOT refers to the FPGA reading bitstream data from different addresses in the external Flash memory MULTIBOOT is supported by all FPGA devices that supports MSPI mode The default Flash start address following FPGA power up is 0x0000 and this address is always used to load the initial bitstream The Gowin Programmer software supports the ability to write multiple bitstreams to external Fla...

Page 77: ...all Working images are erased then the FPGA will continue reading Flash Addresses until the Golden Image is reached In the unlikely event all the Flash images are corrupted the SPI Flash will need to be reprogrammed via the JTAG SSPI interface Figure 6 44 Example of Bitstream Image Distribution in Flash Memory For example Working Image 0x0 resides at the default 0x0000 power on address Working Ima...

Page 78: ...ing the GOWIN EDA tools the user can specify the SPI Flash start address of the next bitstream to be loaded Using the GOWIN EDA software open the Bitstream option dialog box Input the start address for the next Bitstream in the text box following SPI Flash Address as shown in Figure 6 45 Figure 6 45 Input the Start address for the Next Bitstream SPI Flash Programming The Gowin Programmer software ...

Page 79: ...e FPGA Gowin supports configuring multiple FPGAs using a single Flash memory The 1st FPGA is connected directly to the SPI Flash using MSPI mode while the downstream FPGA devices are configured using SERIAL mode The Multi FPGA SPI Flash connection diagram is shown in Figure 6 47 Notes For devices that need to forward data the Wake Up Mode value should be set to 1 Wake Up Mode is usually used in a ...

Page 80: ...duction 6 5MSPI UG290 2 5 2E 71 100 Figure 6 47 Connection Diagram for Configuring Multiple FPGAs via Single Flash 6 5 5 MSPI Configuration Timing MSPI Download Timing is as shown in Figure 6 48 Figure 6 48 MSPI Download Timing ...

Page 81: ...tmclk Time from READY rising edge to first MCLK edge 2 8μs 4 4μs Other than the power requirements the following conditions need to be met to use the MSPI configuration mode MSPI port enable RECONFIG_N is not set as a GPIO during the first configuration after power up or the previous programming Initiate new configuration Power on again or trigger RECONFIG_N at one low pulse Figure 6 49 Multiple F...

Page 82: ...wo built in Flash in Dual BOOT mode The Dual Boot mode configuration flow is shown in Figure 6 50 Figure 6 50 Dual Boot Flow Chart start ready emFlash fail exFlash fail Y N Y end N fail success Y N Note When the MODE value is set to 110 the FPGA first attempts to configure from the external Flash GW1N R 9 and GW1NS series products support four times configuration in all DUAL BOOT modes Start from ...

Page 83: ...e shown in Table 6 17 Table 6 17 CPU Mode Pins Pin Name I O Description RECONFIG_N I internal weak pull up Low level pulse Start GowinCONFIG READY I O High level pulse The device can be programmed and configured Low level Programming configuration for device is prohibited DONE I O High level Successfully programmed and configured Low level Programming and configuration uncompleted or failed MODE 2...

Page 84: ...the first configuration after power up or the previous programming Initiate new configuration Power on again or trigger RECONFIG_N at one low pulse 6 7 1 Configuration Timing Before configuration make sure that MODE 2 0 111 and DONE will be pulled up after configuration If DONE or READY is pulled down the configuration fails In the configuration process data bus D 7 0 is the MSB mode and the FPGA ...

Page 85: ...figured Low level Programming and configuration uncompleted or failed MODE 2 0 I internal weak pull up Configuration mode selection READY rising edge sampling SCLK I Input clock DIN I internal weak pull up Input data DOUT O Output data only used in SERIAL configuration mode when FPGA cascading The connection diagram for the SERIAL mode is shown in Figure 6 53 Figure 6 53 Connection Diagram for SER...

Page 86: ...the device maynot be configured correctly In I2 C Mode Gowin FPGA products are configured by Host via I2 C interface I2 C Mode is one of the configuration modes that use the least number of pins The I2 C mode can only write bitstream data to FPGA and cannot readback data from FPGA devices as such the I2 C mode cannot read information on the ID CODE USER CODE status register and read back check A d...

Page 87: ...s the slave device when the master device is about to communicate with it R W Read Write bit Determines whether the master sends data to the slave 0 or reads data from the slave 1 ACK ACK NACK bit Each frame in the message is followed by an ACK NACK bit and Gowin FPGA returns 0 if correct DATA Data A data has 8bits and the most significant bit is sent first All DATA on the I2C bus is transmitted i...

Page 88: ...te only while the SCL is low Logic 0 has a low voltage level and Logic 1 has a high voltage level as shown in the figure below The list of I2 C mode supported by Gowin FPGA devices is as shown in the table below Mode Device Frequency Address SRAM GW1N 2 IDCode 0x0120681B 100Khz 1 33Mhz 7 b1010_000 Embedded Flash GW1N 2 IDCode 0x0120681B 1 33Mhz 1 7 b1011_000 External Flash Note If you use I2 C to ...

Page 89: ...m file format for confgiuring SRAM is FS fs or Binary bin and the data stream file format for programming the internal Flash is I2C i2c Regardless of the file format the data is sent byte by byte in MSB way Figure 6 57 Process of GW1N 2 Configuring or Programming SRAM Flash Start I2C Start Write Address Write Bitstream Data MSB I2C Stop Stop ...

Page 90: ...ault in the FPGA bitstream file and the security bit is set During the process of data configuration input data is checked in real time The wrong data cannot wake up the device and the DONE signal is pulled down After the configuration of the bitstream with security bit is complete data readback cannot be performed 7 1 Configuration Options Please refer to Figure 7 1 for the related configuration ...

Page 91: ...ly only The Gowin Arora Family of FPGA products support bitstream data encryption using the 128 AES encryption algorithm Please refer to the following steps for the data encryption configuration 1 Enter the encryption KEY KEY in Gowin software interface to generate the bitstream data 2 Enter the decryption key in Gowin Programmer 3 After encrypted bitstream data is loaded into the device FPGA comp...

Page 92: ... back data is 1 7 2 2 Enter Encryption KEY Refer to the steps below to write the encryption keys in Gowin software 1 Open the corresponding project in Gowin software 2 Select Project Configuration Dual Purpose Pin from the available menu options 3 Click BitStream check Enable Encryption only support GW2A and input the key value as shown in Figure 7 2 Figure 7 2 Encryption Key Setting Method After ...

Page 93: ...the Lock command Once you have performed this action any read and write key operations will be invalid the key value cannot be modified and all read bits are all 1 After the decryption key is set the encrypted bitstream data will only work when the data matches the decryption key The key does not affect the non encrypted bitstream data Note The initial value of the Gowin FPGA keys is 0 If a key va...

Page 94: ...k read and write access to the Key Write 1 Write the user defined Key to the text box in the figure above 2 Click Write button 3 Return the validation result after running Read Click Read button to validate the written AES encryption key again The Key that is read from the tool will be displayed in the text box in the figure above Lock Click Lock to lock the read and write permission of Key If it ...

Page 95: ...y All the flows are based on JTAG protocol Check ID CODE Check the device ID to determine whether the JTAG protocol works properly and whether the programing object is correct to avoid misoperation Figure 7 5 Prepare Start Check ID Transmit Read ID Command 0x11 Read 32 Bits ID match Stop Yes No Yes No The sign can be A To read AES key flow B To program AES key flow C To lock AES key or Set Key2 se...

Page 96: ...ation Data Encryption Supported by Arora Family only UG290 2 5 2E 87 98 Read AES Key Figure 7 6 Read AES Key Flow Transmit Read Key Command 0x25 Read 128 Bits Delay 100 ms Stop A Transmit ISC Enable Command 0x15 Transmit ISC Disable Command 0x3A ...

Page 97: ...S Key Flow Lock AES Key Locking the AES Key prevents the Key leakage After locking the AES Key you will not be able to read and configure the AES Key Transmit Program EFuse Command 0x24 Transmit Program Key Command 0x29 Transmit 128bits Delay 800 ms Transmit Read ID Command 0x11 Stop Transmit ISC Enable Command 0x15 Transmit ISC Disable Command 0x3A B ...

Page 98: ...amming Users can configure the bitstream file format in Gowin software 1 Open the Gowin software 2 On the Process tab right click Place Route and then click Configuration Bitstream 3 In the options of Bitstream Format select Text or Binary as shown in Figure 7 9 Transmit Program EFuse Command 0x24 note Start the 2 5 V circuit to get the voltage ready before program efuse Transmit Security Command ...

Page 99: ...n Table 7 1 Table 7 1 Gowin FPGA Products Configuration File Size Max Device Name LUT Max Configuration File Size GW1N 1 S GW1NR 1 GW1NZ 1 1 152 84 KBytes GW1N 1P5 1 584 113 KBytes GW1NS 2 C GW1NSR 2 C GW1NSE 2C 1 728 TBD GW1N 2 GW1NR 2 2 304 113 KBytes GW1N 4 GW1NR 4 GW1NS 4 C GW1NSR 4 C GW1NSE 4C GW1NSER 4C GW1NRF 4B 4 608 217 KBytes GW1N 9 GW1NR 9 8 640 435 KBytes GW2AN 9X 10 368 887 KBytes GW2...

Page 100: ...s powered on it can read bitstream files from the external SPI Flash and then complete the configuration The default frequency of reading configuration file is 2 5 MHz One bit is read at each SPI clock so the required loading time can be calculated according to the file size The clock frequency of reading SPI Flash in MSPI mode can be up to 125 MHz Note that the FastRead_n pin should be grounded a...

Page 101: ... Frequency of Autoboot Max Loading Frequency of MSPI GW2A 55 55C 125 MHz GW2A 18 18C GW2AR 18 18C GW2ANR 18C GW1N 1 26 MHz GW1N 1S GW1NS 2 33 MHz 120 MHz GW1NSR 2 GW1NS 2C GW1NSR 2C GW1NSE 2C GW1NZ 1 40 MHz GW1N 2 GW1N 2B GW1NSER 4C GW1NS 4 GW1NSR 4 GW1NS 4C GW1NSR 4C GW1N 4B GW1NR 4B GW1NRF 4B GW1N 4 GW1NR 4 GW1N 6 GW1N 9 GW1N 9C GW1NR 9 GW1NR 9C ...

Page 102: ...f LUT4 Max Configuration File Loading Time ms when frequency 2 5 MHz default frequency Loading Time ms when Frequency 25 MHz Loading Time ms when Frequency 31 25 MHz 1 152 84 KBytes 34 4 3 4 608 217 KBytes 88 9 7 8 640 435 KBytes 178 17 14 What is listed above is the reference of loading time From power on to configuration completion of the device in addition to the configuration time there are al...

Page 103: ... used to configure Gowin FPGA by following the steps outlined below 1 Connect the device that needs to be configured 2 Start Gowin programmer to start scanning and the connected FPGA devices can be identified automatically 3 Select the bitstream and configuration mode to configure the device During the process outlined above Gowin programmer will read the connected device ID first and then compare...

Page 104: ... interface After Configuration After configuration the device bitstream will be loaded to the SRAM or on chip Flash according to the configuration mode selected On chip Flash is supported by the LittleBee Family of FPGA products only If the data is loaded to the SRAM Gowin software will set the security bit automatically in the process of bitstream generation and no user can read SRAMs If the data...

Page 105: ...L file for device testing The short chain is mainly used to erase and read and write the external Flash on the FPGA chain To perform a boundary scan follow the steps outlined below 1 Connect the FPGA development board to the PC and then power up 2 Open Gowin programmer and scan the connected devices 3 Double click in the Operation field and select External Flash Mode and the related bscan operatio...

Page 106: ...ematic Diagram The boundary scan operation can only be performed on the external Flash of FPGA and cannot be used to program the embedded Flash or SRAM This operation is irrelevant with the FPGA MODE value but it is slower than that of the external Flash programming via JTAG ...

Page 107: ...n are as shown in Table 9 1 Gowin FPGA can read data from this Flash Table 10 1 SPI Flash Operation Instruction Operation Instruction Read 0x03 Fast_Read 0x0B Note The Flash read instructions supported by Gowin FPGA must have at least one 03 or 0B Use the regular reading instruction if the clock frequency is no higher than 30 MHz Use the fast reading instruction if the clock frequency is higher th...

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