6 Configuration Mode Introduction
6.2 JTAG Configuration
UG290-2.5.2E
29(98)
Instruction register (IR) scan;
Data Register (DR) scan.
During the IR scanning operation, in Shift_IR state, the data or
instructions are sent to the IR in the LSB way. The lower data bits are sent
first. The instructions will be all sent when the sate machine returns to
Run-Test-Idle, as shown in Figure 6-8
During the data register scanning operation, the data or instructions
are sent to the DR in the Shift_DR state, as shown in Figure 6-9. The data
is sent in LSB way or MSB way depending on specific operations.
Figure 6-8 Instruction Register Access Timing
Figure 6-9 Data Register Access Timing
Note!
The total length of the instruction register is 8 bits in the GW1N(R) and GW2A(R)
series of the FPGA;
The length of the data register can vary depending on the selected register.
Read ID CODE Instance
ID Code, i.e. JEDEC ID Code, is a basic identification of FPGA
products.
The length of the Gowin FPGA ID Code is 32 bits. The ID Codes of the
FPGA are listed in the following table.
Table 6-5 Gowin FPGA IDCODE
Gowin FPGA Device Family IDCODE
