5 Configuration Pin
5.1 Configuration Pin List and Reuse Options
UG290-2.5.2E
14(98)
Pin Name
I/O
JTAG
GowinCONFIG
AUTO
BOOT
I
2
C
SSPI MSPI
DUAL
BOOT
SERIAL CPU
CLKHOLD_N/DIN
I
√
√
√
WE_N/DOUT
O
√
√
MI /D7
I/O
√
√
MO /D6
I/O
√
√
MCS_N /D5
I/O
√
√
MCLK /D4
I/O
√
√
FASTRD_N /D3
I/O
√
√
SI /D2
I/O
√
√
SO /D1
I/O
√
√
SSPI_CS_N/D0
I/O
√
√
SCL
I
√
SDA
I/O
√
Note!
For the configuration modes supported by different devices, please refer to
3Configuration Modes;
Please refer to 6 Configuration Mode Introduction for the definition of each pin in
different configuration modes.
5.1.2
Configuration Pin Reuse
To maximize the utilization of I/O, Gowin FPGA products support
setting the configuration pins as GPIO pins. Before any configuration
operation is performed on all series of Gowin FPGA products after power
up, all related configuration pins are used as configuration pins by default.
After successful configuration, the device enters into user mode and
reassigns the pin functions according to the multiplex options selected by
the user.
Note!
When setting the pin multiplexing option, ensure the external initial connection state of the
pins does not affect the device configuration. Isolate the connections that affect the
configuration first, and then wait to modify them in user mode.
The reuse options for the configuration pins are detailed in Table 5-2.