Chapter 4 Software Index
4-40
Parameter Group 7 - Analog input signal operation mode
Analog Input Signal Operation Mode:
7-00:AIN Gain(%) 0 - 200
7-01:AIN Bias(%) 0 - 100
7-02:AIN Bias Selection: 0000:positive 0001:Negative
7-03:AIN Slope: 0000:positive 0001:Negative
7-04: AIN signal verification Scan Time (AIN, AI2) 1–100 (
×
4mSec)
7-05: AI2 Gain (%)(S6) 0 – 200
1.
7-02 = 0
：
0V(0mA) corresponding to Lower Frequency Limit.
，
10V (20mA) corresponding to Upper
Frequency Limit.
2.
7-02 = 1
：
10V(20mA) corresponding to Lower Frequency Limit
，
0V (0mA) corresponding to Upper
Frequency Limit.
3
.12-6 = 0
：
0~10V(0~20mA)
F = I * ( 3 - 0 0 ) / 2 0 I > = 0
；
S W 2 =
Ｉ
o r F = V * ( 3 - 0 0 ) / 1 0 V > = 0
；
S W 2 = V
= 1
：
2~10V(4~20mA)
F = ( I - 4 ) * ( 3 - 0 0 ) / 1 6 I > = 4
；
S W 2 =
Ｉ
F = 0
I < 4
F = ( V- 2 ) * ( 3 - 0 0 ) / 8 V > = 2
；
S W 2 = V o r
F = 0 V < 2
The setting of figure 1: The setting of figure2:
7-00
7-01
7-02
7-03
7-05
7-00
7-01 7-02
7-03
7-05
A 100
﹪
50%
0
0
100%
C 100
﹪
50%
0 1
100%
B 100
﹪
0%
0
0
100%
D
100
﹪
0%
0
1
100%
The setting of figure 3: The setting of figure 4:
7-00
7-01
7-02
7-03
7-05
7-00
7-01 7-02 7-03
7-05
E
100
﹪
20%
1
0
100%
F 100
﹪
50%
１
1
100%
3.
The inverter reads the average value of A/D signals once per (7-04×4ms). Users can determine scan
intervals according to noise in the environment. Increase 7-04 in noisy environment, but the respond
time will increase accordingly.
Upper Frequency Limit
(3-00=60)
Upper Frequency Limit
(3-00=60)
Hz
V
60Hz
30Hz
0Hz
E
2V
(4mA)
10V
(20mA)
Bias
0%
-50%
-100%
Figure 3
Hz
V
60Hz
30Hz
0Hz
F
5V
10V
(20mA)
Bias
-0%
-50%
-100%
Figure 4
0V
(0mA)
Upper Frequency
Hz
V
60Hz
30Hz
Bias
0Hz
0V
(0mA)
A
B
5V
10V
(20mA)
100%
50%
Figure 1
Upper Frequency Limit
(3-00=60)
Hz
V
60Hz
30Hz
0Hz
C
D
5V
10V
(20mA)
Bias
100%
50%
Figure 2
