GE UR series, Instruction Manual

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GE Multilin L60 Line Phase Comparison System 8-27
8 THEORY OF OPERATION 8.1 OVERVIEW
8
The logical signal that marks the positive polarity (P) is asserted as long as the mixed current is greater than 0.005 pu of
the CT nominal. The logical signal that marks the negative polarity (N) is asserted as long as the mixed current is less than
–0.005 pu of the CT nominal.
To ensure security and dependability for blocking schemes, especially during low current conditions when pulses might be
shortened, square pulses are created as follows.
(EQ 8.8)
Figure 8–22: FORMATION OF SQUARE PULSES FOR TRIPPING AND BLOCKING SCHEMES
The operation for blocking schemes insures reliable blocking pulses in cases where the operating current is close to the
squaring pickup constant (0.005 pu). If the operating signal triggered positive square pulse once it crossed the positive
threshold, then it stays within the deadband (between
and ) and the blocking
pulse is reset in one cycle.
The phase comparison principle faces security problems when fed from externally summed currents in two-breaker applica-
tions. To maintain the excellent immunity to CT saturation of the ‘original, single-breaker’ phase comparison principle, the
two currents must be processed individually and both the phase and magnitude information used to detect the through fault
condition.
The dual breaker logic consolidates two pieces of information: fault detector flags signaling the rough current levels and the
phase pulses signaling current direction.
The fault detector flags are ORed between the two breakers (breakers 1 and 2) as follows.
FDL = FDL1 OR FDL2
Where FDL1 and FDL2 are ORed mixed current signals and the advanced fault detectors are as per the 87PC logic, and:
FDH = FDH1 OR FDH2
Where FDH1 and FDH2 are ORed mixed current signals and the advanced fault detectors are as per the 87PC logic.
The rationale behind this logic is that regardless which breaker (or both) carries a current, the elevated current condition
(FDL) shall be declared to signal permission or blocking as per the scheme type and fault location. The trip supervision
condition (FDH) is processed in a similar manner.
The ‘pulse’ combination logic ensures security and dependability. With this respect, a distinction must be made between
tripping and blocking schemes. The following figure illustrates the dual breaker logic for permissive (section a) and blocking
(section b) transmit schemes.
PICKUP_LOC
1P_RAW
i
1_ MIX
0.005 2 CT
1pu
× × >
=
DROPOUT_LOC
1P_RAW
i
1_ MIX
0.005 2 CT
1pu
× ×
–
<
=
PICKUP_LOC
1N_RAW
i
1_ MIX
0.005 2 CT
1pu
× ×
–
<
=
DROPOUT_LOC
1N_RAW
i
1_ MIX
0.005 2 CT
1pu
× × >
=
831803A2.CDR
Positive
Negative
Tripping schemes
Positive
Negative
Blocking schemes
2 pu 0.005
´
2 pu –0.005
´
2 pu
´
2 pu
´
0.005
–0.005
0.005
–
2 CT
1pu
× ×
0.005 2 CT
1pu
× ×