Fujitsu DevKit16 User Manual Download | Manualshive

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89

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these facts.

•

An error was found in the chapter “Mainboard
description” – the Prototype connector had
different pinout than the one in the schematics
(the schematics are correct, however)

V1.25

04.03.2000

An error in the FLASH end address in the SWAP
mode - on the page 73, FLASH ends at 140000H
(not 180000H)

V1.26

11.05.2000

•

In the chapter 4, paragraph “Get it running”, the
Softune Workbench is recommended to be run
first (with the “Demo.LEDs” project). However,
the Softune *.PRJ file is generated by the PE
during codesign process, so the PE must be run
first. The paragraph was updated to reflect this
change. Also, the communication settings for
the Softune debug monitor are described there

•

In the chapter 6, the section “How to burn the
CPU FLASH without Devkit16” was added

•

The chapter “What to do if” was updated

V1.27

18.12.2000

•

The pinout of the A/D connector on page 51 has
been corrected

•

MCU board schematics has been corrected

V1.28

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Summary of Contents for DevKit16

Page 1: ...FUJITSU MICROELECTRONICS EUROPE Development tools for 16LX Family DevKit16 User Guide Version Version Version Version 1 28 ...

Page 2: ...D E V E L O P M E N T T O O L S F O R 1 6 L X F A M I L Y DevKit16 User Guide ...

Page 3: ...o run software 10 HW installation 10 Default settings for SOFTUNE 11 Default settings for Processor Expert TM 12 DevKit16 SW overview 12 Softune WorkBench 12 PROCESSOR EXPERT TM 12 SW installation 15 Get it running 16 Design application with Processor Expert TM and run it using Softune Workbench monitor debugger 16 Run first application using Softune WorkBench and FUJITSU monitor debugger 16 Run f...

Page 4: ...burn user program into the FLASH 31 How to burn the SOFTUNE debug monitor 32 How to burn the PE debug kernel 33 How to burn the CPU FLASH without Devkit16 34 Running burned program 35 FlashTool commands parameters 35 Notes 35 Error Messages 36 Processor Expert beans IntFLASH and ExtFLASH runtime support of FLASH access and design time checks 37 CPU board for MB90F543 description 38 CPU Board overv...

Page 5: ... 63 Add on FPGA output only port 64 User UART 65 I2 C 67 Keyboard controller 70 LED display 71 FPGA EEPROM 71 System control registers 73 Default jumper settings 81 What to do if 82 Get the most from DevKit16 84 Download the current SW and HW updates 84 Check the net for newest beans 84 DevKit16 Power Supply Requirements 85 Warranty and Disclaimer 86 Revision and Error List 88 Appendix 90 ...

Page 6: ...cluded in DevKit16 provides brief information which HW and SW tools are included in package Chapter 3 DevKit16 features and technical specification provides necessary technical and operational information Chapter 4 Getting Started explains how to run your first application on DevKit16 including all steps and HW and SW installation Chapter 5 Debug application explains methods how to debug your appl...

Page 7: ...rces MCU Softune Workbench and tools FUJITSU Micros CD ROM Ver 3 0 or higher Processor Expert TM and tools DEVKIT16 Software CD ROM Parts and other HW components datasheets of their producers W H E R E T O F I N D N E W S O P T I O N S N E X T B E A N S N E X T C P U B O A R D S L A T E S T F A Q A N D S U P P O R T Please visit DevKit16 WEB site www processorexpert com devkit16 for news and givea...

Page 8: ...ease call your nearest FUJITSU subsidiary or authorized FUJITSU distributor According to your request there are available CPU boards with soldered CPU or with 100pin socket Socket versions are intended to support FUJITSU emulator S O F T W A R E Two CDs are included in package CD 1 FUJITSU Micros Documentation Software CD 2 DevKit16 Software CD 1 includes all the MCUs informations Softune Workbenc...

Page 9: ...7 7 7 7 Fujitsu Monitor Debugger for MB90F543 to provide debug for Softune on DevKit16 Processor Expert TM Bean Wizard Processor Expert TM Debug Kernel for MB90F543 DevKit16 FLASH Programming tool ...

Page 10: ...ive most requested HW development kits features 5 I N 1 C O M B O O F H W F E A T U R E S Standard Starter Kit FLASH Development Kit CAN Development Kit Application Board Rapid Hardware Prototyping A D D I T I O N A L H W F E A T U R E S Open HW architecture Keeps CPU resources available for user Supports single chip debug for CPUs from 16LX family with External Bus Interface Supports jumperless C...

Page 11: ...us provides compatibility for Main board Device bus is located on CPU board and provides compatibility with use of CPU peripherals This allows to provide low cost CPU personality boards which are compatible with the Interface and Device Bus and reflects different MCU pin layout Expansion buses connectors User Prototype connector with user chip select and bus signals FPGA User Programmable Pins 40 ...

Page 12: ...n combination with powerful software tools including debuggers it provides enough capacity for fast application development T E C H N I C A L R E Q U I R E M E N T S T O R U N S O F T W A R E Please check the specifications which are already available for Fujitsu Softune WorkBench on FUJITSU CD ROM The Processor Expert TM conditions are available in its README TXT file H W I N S T A L L A T I O N ...

Page 13: ...d lights on Green LED on Main board lights on without blinking When you experience something different please check your power supply or try to find solution in chapter How to When this step went OK switch power off and connect DevKit16 with PC using attached cable to USER FPGA UART and a free serial port on PC which is not used by other device in PC D E F A U L T S E T T I N G S F O R S O F T U N...

Page 14: ...une Workbench provides all the classic tools In order to use it for application debug on DevKit16 FUJITSU Monitor Debugger must be installed in Main board FLASH to establish communication between PC and the debugged target application P R O C E S S O R E X P E R T T M Processor Expert TM provides its own workbench including debugger For the program compilation it uses Softune tools compiler assemb...

Page 15: ...to the required timing parameters and accuracy in property Interrupt period Figure Selecting a CPU timing resource for the TimerInt bean Figure Setting the interrupt period of the TimerInt bean If you need functionality you can choose appropriate bean and PE offers the possible MCU resources ...

Page 16: ...can use more instances of it and each of these instances can hold different setting This makes the application design time with Processor Expert and any microcontroller very short First choose and setup CPU bean add another ones modify their properties select methods and events and choose Codesign Processor Expert generates all code from beans according your settings which is well commented You ca...

Page 17: ...bean reference type for this bean This allows in design time for new bean access its parents properties and define physical connection pins or timer resources Additionally new bean will have its own properties and methods Methods can be constructed using parent beans methods The same situation is with events Don t be afraid about the complexity of this simply choose from Processor Expert Tools men...

Page 18: ...O R D E B U G G E R Run Processor Expert TM choose Open existing project from startup screen and select under PE Projects Demo Leds LEDS pe Please choose Options Environment and Project Options This opens Options window on Environment options page Uncheck item Succesful Make and Build automatically starts PE debug and confirm OK Choose Tools Build or Ctrl B After successful Build choose Tools Fuji...

Page 19: ...choose Tools Burn PE Debug Kernel IR This will run DevKit16 FLASH Programming tool with correct parameters in Auto program mode For more detailed description about burning the PE debug kernel refer to chapter 6 section How to burn the PE debug kernel You should change the Main board System Configuration DIP switch as follows setting for CPU FLASH programming mode Set the J1 jumper to the 2 3 posit...

Page 20: ...c LEDs on Main board If there is an error Processor Expert provides approach to detect it Double click on error message s inside error window If the reason is a component you ll be navigated to it by selecting bean in Project panel and opening its Bean Inspector Item related to error is marked by red color so related Inspector s page and its item could be located The usual problem appears when you...

Page 21: ...t Demo Tutorial Open Processor Expert from Window s Start menu Open new project Press button Open new project on startup panel or use command in main menu File New project Select CPU configuration There are several prepared projects included in the Processor Expert These projects contain typical CPU settings and two configurations one configuration for debug and second one for release final versio...

Page 22: ...dge Select methods Enable Disable Select events OnInterrupt Codesign If there are no errors in your project select command main menu Codesign Codesign or press Ctrl G to codesign code All drivers are generated during codesign Note Processor Expert requires to save the project before codesign You can do it using command File Save project or press Ctrl S If you do not save project before codesign Pr...

Page 23: ...k generated and user code Note Processor Expert requires to save all files in internal editor You can do this unis command editor local menu File Save or press Ctrl S If you check option main menu Options Environemnt Options Autosave file before running codesign or external tool Processor Expert saves all files automatically Debug Check the settings of jumpers on the DevKit16 connect your PC with ...

Page 24: ...rt TM environments S O F T W A R E D E B U G G E R S Software debuggers provide good ratio functionality cost The target system is equipped with small debug kernel which provides back end for PC Debugger front end CPU software interrupts are used for breakpoints stepping functions To realize this function user code must be located in RAM type memory 16LX MCUs provides ROM Correction Modules periph...

Page 25: ...itation is that breakpoint uses external interrupt line of CPU which should run on top priority The software debugger kernel is started after reset from Main board FLASH in UMB then RAM is swapped with FLASH which means RAM appears on UMB and FLASH with kernel in LMB Then the application code can be downloaded into Main board RAM in UMB The application is debugged at addresses where it will burned...

Page 26: ...bug so CPU UART s are available for user User application is debugged in final place in memory Frontend is Fujitsu Softune WorkBench For user program is available area 0F82000H to 0FFFFFFH Interrupt vector table IVT is located on 0FFFC00H For Mon Debugger code is reserved FLASH segment 0FFH UMB 13H LMB IVT entries which cannot be overwritten for 543 CPU reset ROM Correction exception 15 external i...

Page 27: ... PE debug kernel was developed as very tiny 3 5KB but powerful solution which features with high speed communication and capacity for on demand runtime access to application variables This access is provided by FPGA UART interrupt which is running on selected priority so no CPU timer and its periodic ISR overhead is used There is list of another advantages of PE Debug kernel Communication speeds u...

Page 28: ... its value For user program and data is available area 0F82000H to 0FFFFFFH Interrupt vector table is located on 0FFFC00H Kernel code starts at 0FFC000H or 13C000H respectively in Main board FLASH IVT entries which cannot be overwritten for 543 CPU 8 reset 9 ROM Correction INT9 10 exception 15 external interrupt 0 1 No more CPU resources are used in PE Debug kernel Breakpoints references are store...

Page 29: ...128kB provided by the MB90F543 CPU O V E R V I E W O F D E V K I T 1 6 F L A S H P R O G R A M M I N G T O O L DevKit16 FLASH Programming Tool provides standard operations for CPU Internal FLASH memory Main board FLASH or both When the PC DevKit16 communication uses the Mainboard FPGA UART the programming operation can run on the highest speed of PC serial port 115200Bd Chapter 6 ...

Page 30: ...T A L L I N G T H E F L A S H P R O G R A M M I N G T O O L The FLASH programming tool Flashtool is installed during Processor Expert installation User can even choose not to install the PE but the FLASH tool only In such a case only files and directories necessary for using Flashtool with Devkit16 is installed including both Fujitsu debug monitor and PE debug kernel ABI files The latest update fo...

Page 31: ...ted range of memory in hex numbers Search Searches for user values in defined memory range Open abs Loads the absolute project which contains the user program prepared for burning into the FLASH Write file Writes the data from abs file into the selected FLASH memory Read compare Compares data in abs file and data in FLASH memory If a difference is found user is informed After successful comparing ...

Page 32: ...ou have any version of Flashtool prior to the 1 2 you can download the latest Flashtool installation package from the PE Web site If you use standard Devkit16 CPU board in connection with Mainboard without any additional HW that could cause the AD bus contention set the External bus free radio button to Yes in Flashtool If you use a standalone CPU board with a RS 232 adaptor on the K7 connector or...

Page 33: ...emory maps see the UserGuideDevkit16 PDF manual chapter Mainboard Programmer s Reference Now you can click on the button Connect Flashtool is now ready to start the desired operations N E C E S S A R Y D E V K I T 1 6 M A I N B O A R D H W S E T T I N G S PC must be connected to the Devkit16 USER UART connector The J1 jumper must be in the 2 3 position the PE debugger position and all the other ju...

Page 34: ... flow control mode J9 must be in the 2 3 position otherwise some data can be lost during the communication To burn the Softune debug monitor to the Devkit16 external FLASH follow these steps 1 From the PE environment For the 38400 variant From the Tools menu choose the item Burn Softune Monitor for MB90xxx into Devkit16 Ext FLASH 38400 Bd where xxx stands for the CPU type e g 543 or 497 For the 96...

Page 35: ...it is suitable for user applications that require maximum free space in the external memory The second PEdebugKernel_ER_xxx abi where xxx is the CPU type uses external RAM and it is applicable in cases when user wants to debug application that uses the internal RAM Because the debugging in internal RAM does not allow using the FPGA breakpoint logic some features of the PE debugger will not work e ...

Page 36: ...inboard This is important in the moment when you have an application board of your own and you want to verify if the application you have written is working well on your board The application board must have a serial RS 232 interface connected to the CPU UART interface dedicated to the communication in the serial asynchronous mode Refer to the following table to find out which CPU uses which UART ...

Page 37: ...shTool to reset the mainboard in the right mode without changing switches 3 How does the FlashTool know the right mode This information about the mode is stored in the abs file exactly in the vector table F L A S H T O O L C O M M A N D S P A R A M E T E R S FlashTool exe move from to cfg filename 1 move data which are placed in segment from will be placed into the segment to The from to are hexad...

Page 38: ...H this code cannot be burned Set the right FLASH or recompile program to correct addresses The abs file has been compiled for internal FLASH the user code is prepared for running in internal FLASH but different mode is selected Set the right mode The abs file has been compiled for external FLASH the user code is prepared for running in external FLASH but different mode is selected Set the right mo...

Page 39: ... not responding try repeat programing cycle again Time out kernel is not responding restart the mainboard Unknown error unexpected error during communication P R O C E S S O R E X P E R T B E A N S I N T F L A S H A N D E X T F L A S H R U N T I M E S U P P O R T O F F L A S H A C C E S S A N D D E S I G N T I M E C H E C K S These beans from Processor Expert TM accomplish the tasks with programmi...

Page 40: ...DIP to OFF C P U B O A R D O V E R V I E W CPU personality board is designed as low cost board which provides compatibility on Interface Bus and the Device Bus level for different CPUs Additionally headers pin compatible to CPU pins are provided connectors for all CPU pins a Bus Interface connector for main board connection a Device Bus connector a power supply supervisor IC with reset generation ...

Page 41: ...nterface connector This connector serves for connecting the CPU board to the Main board connection Note For the pinout of this connector please see the attachments section of this manual K2 Device Bus connector This connector provides connection CPU peripherals Device Bus GND CPU Pins Jumpers VCC Hi speed crystal Low speed crystal RST HST DC power supply CPU serial interface DIP switches Interface...

Page 42: ...ers on the Mainboard Also when the Async Serial programming mode is set on the Mainboard System control DIP switches the FPGA UART RS232 driver is connected to UART0 or UART1 depending on the setting of the UART0 1 switch after reset If you want to use K7 also in that case remove the 3 4 5 6 jumpers on the J23 as well K9 power supply connector Before applying the power to the Devkit16 check the po...

Page 43: ...AN1 39 AN3 41 AN4 43 AN6 45 TIN0 47 MD0 49 32 INT7 34 AVCC 36 AVR 38 AN0 40 AN2 42 Vss 44 AN5 46 AN7 48 TOT0 50 MD1 MD2 51 IN0 53 IN2 54 IN4 57 OUT2 IN6 59 PPG0 61 PPG2 63 OUT0 65 TIN1 67 INT0 69 INT2 71 TX0 73 TX1 75 52 HST 54 IN1 56 IN3 58 IN5 60 OUT3 IN7 62 PPG1 64 PPG3 66 OUT1 68 TOT1 70 INT1 72 INT3 74 RX0 76 RX1 RST 77 78 PA0 X1A 79 80 X0A VSS 81 X1 83 AD00 85 AD02 87 AD04 89 AD06 91 AD08 93...

Page 44: ...GND is connected to CPU s AGND pin J5 Analog Reference Voltage for CPU When SHORT board s VCC is connected to CPU s AVR pin When removed the voltage at the AVR pin is set to 4V J6 Analog Reference Voltage for CPU When SHORT board s GND is connected to CPU s AVR pin When removed the voltage at the AVR pin is set to 0 9V J7 J8 J9 UART0 1 selection for the K7 connector These jumpers select which of t...

Page 45: ...mory even in the case when CPU itself doesn t provide the I2 C interface When both of these jumpers are SHORT the CPU s HRQ signal is connected to the Mainboard s SDA signal via J19 and HAK signal is connected to SCL signal An user can then program the HAK HRQ signals to behave as I2 C interface J15 J16 Low speed XTAL jumpers When short these jumpers connect the 32 768 kHz crystal to the Bus Inter...

Page 46: ...FF OFF External vector mode 0 External 8 ON ON OFF OFF OFF External vector mode 1 External 16 ON OFF ON OFF OFF External vector mode 2 External 16 ON OFF OFF OFF OFF Internal vector mode Internal Mode data OFF ON ON X X Reserved OFF ON OFF X X Reserved OFF OFF ON ON ON Async serial programming OFF OFF OFF X X Reserved 4 S R if ON this switch connects the RES pin of the K7 connector to the CPU s RS...

Page 47: ...ough this jumper J4 The CPU AGND supply pin is connected to the GND through this jumper J5 The CPU AVR pin is connected to the 5V voltage through this jumper J6 The CPU AVR pin is connected to the 0V voltage through this jumper J7 9 The CPU UART1 signals are connected to the K7 connector J13 The board is powered from the 5V from the power supply voltage regulator J19 The CPU HRQ pin is connected t...

Page 48: ...l model with mirror of bank FF to bank 0 for area 4000H 0FFFFH additional four ports to be used instead of CPU s P0 P1 P2 P3 in order to support CPU single chip mode debugging using external bus mode of CPU three RS232 interfaces 2 dedicated for CPU one for Main board UART DB9 two high speed CAN drivers and connectors DB9 CAN and RS232 drivers can be replaced by user ones serial EEPROM 1kx8 24C08 ...

Page 49: ...ter including AD trigger references power supply prototype header for prototype boards with user chip selects amplifier and speaker USB connector not mounted by default Simulated CPU ports header Custom IC FPGA User Programmable Pins connector Automatic serial interface change from User UART to CPU UARTx when CPU FLASH programming mode is entered Interface bus UART1 User UART UART0 CAN1 CAN1 Keybo...

Page 50: ...he Mainboard Programmer s Reference chapter C A N I N T E R F A C E S There are two CAN interfaces CAN0 and CAN1 The 82C250 chips are used to interface the CPU CAN0 and CAN1 signals to a CAN network The P3 P4 potentiometers are used to control rise and fall slope of the CANH CANL signals and the standby mode of the 82C250 chip To set the high speed mode of the 82C250 interface set the P3 P4 potent...

Page 51: ...ard for example the LED is blinking with approximately 1s period Serial line reset LEDs D10 D11 if the serial line reset function is enabled by appropriate jumpers see the Serial line reset jumpers description in this chapter and the reset is activated by serial line the LED will shine The D10 diode is connected to the UART0 1 serial line reset the D11 is connected to the USER UART A U D I O A M P...

Page 52: ...nnector This connector allows the user to connect his prototype board to the AD bus of the MB90F543 processor The description of the pins follows K10 Simulated CPU ports These two connectors contain the simulated CPU ports P0 P3 SP0 0 1 SP0 2 3 SP0 4 5 SP0 6 7 SP1 0 9 SP1 2 11 SP1 4 13 SP1 7 15 2 SP0 1 4 SP0 3 6 SP0 5 8 SP0 7 10 SP1 1 12 SP1 3 14 SP1 5 16 SP1 6 SP2 0 1 SP2 2 3 SP2 4 5 SP2 6 7 SP3 ...

Page 53: ... shown on the next figure UP0 1 UP2 3 UP4 5 UP6 7 UP8 9 UP10 11 UP12 13 UP14 15 2 UP1 4 UP3 6 UP5 8 UP7 10 UP9 12 UP11 14 UP13 16 UP15 UP16 17 UP18 19 VCC 21 UP20 23 UP22 25 UP24 27 UP26 29 UP28 31 18 UP17 20 UP19 22 GND 24 UP21 26 UP23 28 UP25 30 UP27 32 UP29 UP30 33 UP32 35 UP34 37 UP36 39 34 UP31 36 UP33 38 UP35 40 UP37 AVCC 1 AGND 3 AVR 5 ADTG 7 AN0 9 AN2 11 AN4 13 AN6 15 2 AVCC 4 AGND 6 AVR 8...

Page 54: ...female type The pinout is following 1 NC 2 RX 3 TX 4 DTR Reset 5 GND 6 DSR 7 RTS 8 CTS 9 NC K17 PC AT keyboard connector This connector is of the DIN 5 type 1 CLOCK 2 DATA 3 NC 4 GND 5 VCC K19 USB connector The type of the USB connector is B series This allows connecting the board to a PC computer using a standard USB cable 1 VBUS 2 D 3 D 4 GND 5 SHLD Note None of the USB interface parts are mount...

Page 55: ...nector allows connecting an external speaker S W I T C H E S System control DIP switches These switches are used for choosing the initial mode of the CPU after the hard reset caused by power on or the Main board reset button 1 UMD0 2 UMD1 3 UMD2 4 FLASH8 16 5 ADR IO 6 SWAP 7 UART0 1 8 UKEY 1 UMD0 2 UMD1 3 UMD2 The setting of these switches affects the mode of the processor after reset when the Mai...

Page 56: ...ON the external FLASH memory interface is configured to 16 bit mode 5 ADR IO If this switch is ON the A16 A23 CPU pins can be switched to general I O mode Any memory access above the 00FFFFh address is mirrored to the 4000h FFFFh area The decode logic FPGA ignores the A16 A23 address signals and the MirrorFF bit setting This switch allows to use the port P2 A16 A23 signals as general I O without g...

Page 57: ...ility reasons the User key state and the User switch state are logically OR ed to form the value of the USW bit in the SCDS register address C0H Therefore during the reset holding the User key will have the same effect as switching the USW to ON though this OR ing will not be supported in the future so the USW and UKEY will be totally independent The state of the User Key can be still independentl...

Page 58: ...2 interfaces and connect an serial interface of his own to these signals e g a MIDI interface J21 pinout Factory default setting 3 4 short 5 6 short The GND and VCC signals are provided as supply pins for the user built serial interface J22 pinout Factory default setting 3 4 short 5 6 short The GND and VCC signals are provided as supply pins for the user built serial interface 8 from RS2320 output...

Page 59: ... of these two ports the reset polarity of the DTR line can be choosen J5 Port selection UART 0 1 for the Serial line reset In 1 2 position the DTR0 line of the UART0 RS 232 interface is connected to the J21 pin 8 In 2 3 position the DTR1 line of the UART1 RS 232 interface is connected to the J21 pin 8 Note the selected DTRx line is connected to the UART reset logic only if there is a jumper in the...

Page 60: ...connected to serial EEPROM and I2 C connector as well J14 SCL source selection In the 1 2 position the FPGA I2 C interface is selected as the source for the SCL signal In 2 3 position the CPU s I2 C interface is selected J15 SDA source selection In the 1 2 position the FPGA I2 C interface is selected as the source for the SDA signal In 2 3 position the CPU s I2 C interface is selected J13 WP setti...

Page 61: ...X0 and RX1 line of both CAN interfaces is connected to the INT4 J25 J24 CPU CAN signals to CAN drivers connection jumpers These jumper headers are intended to provide access to CPU s CAN0 and CAN1 interface signals An user can disconnect these signals from the PCA82C250 CAN bus transceivers and connect them to a CAN bus transceiver of his own The pinout of J25 J24 is following J25 pinout Factory d...

Page 62: ...le NOTE The XMODE signal is connected also to the pin 5 of the FPGA programming connector K13 so when using a special user made cable it is not necessary to use the J6 jumper J11 SDA to FPGA EEPROM DIN connection When SHORT the FPGA EEPROM DIN pin is connected to the SDA signal on the Mainboard J12 SCL to FPGA EEPROM CCLK connection When SHORT the FPGA EEPROM CCLK pin is connected to the SCL signa...

Page 63: ... G I S T E R A D D R E S S E S A N D C H I P S E L E C T S FPGA I O space is mapped to CPU bank 0 and starts from 0C0H System Control Registers 0C0H 0C8H I2 C 0C9H 0CFH UART 0D0H 0D3H Add on FPGA output only port 0D7H Simulated CPU ports 0D8H 0DFH Add on FPGA ports 0E0H 0E7H Keyboard Controller 0EAH 0EBH FPGA EEPROM 0EFH WWLED 0E8H 0E9H CSUSERIO 0F0H 0FFH The CSUSERIO signal is generated by the FP...

Page 64: ...1 P30 00 H R W Note R W for I O ports means the following Input mode Read The level at the corresponding pin is read Write Data is written to an output latch but not to the pin Output mode Read The level at the corresponding pin is read In most cases it will be the value written to the pin as last the only exception can happen when the pin is erroneously pulled hard to VCC or GND Write Data is wri...

Page 65: ... are provided with FPGA content version 1 and can be found on FPGA User Programmable Pins connector Registers Base Address 0000E0H 1 Port data registers PDR4 7 6 5 4 3 2 1 0 Initial value Access Address E0H P07 P06 P05 P04 P03 P02 P01 P00 00 H R W PDR5 15 14 13 12 11 10 9 8 Initial value Access Address E1H P17 P16 P15 P14 P13 P12 P11 P10 00 H R W PDR6 7 6 5 4 3 2 1 0 Initial value Access Address E...

Page 66: ...is set to 1 the pins work as outputs of the register The pinout for add on ports is following R W for I O ports means the following Input mode Read The level at the corresponding pin is read Write Data is written to an output latch but not to the pin P00 1 P02 3 P04 5 P06 7 P10 9 P12 11 P14 13 P16 15 2 P01 4 P03 6 P05 8 P07 10 P11 12 P13 14 P15 16 P17 P20 17 P22 19 VCC 21 P24 23 P26 25 P30 27 P32 ...

Page 67: ...D21 D20 00 H W DDR7 15 14 13 12 11 10 9 8 Initial value Access Address E7 H D37 D36 D35 D34 D33 D32 D31 D30 00 H W When reading the register last value written to it is returned Pins are controlled as described below 0 Input mode 1 Output mode Note The port direction registers are WRITE ONLY Pull up resistors 47K are internally connected to port pins U S E R U A R T The User UART has the mimic of ...

Page 68: ...mit Buffer Empty Interrupt If this bit is set the interrupt INT1 is activated whenever the THRE bit of the LSR register goes high Bit 5 ERBEI Enable Receive Buffer Full Interrupt If this bit is set the interrupt INT1 is activated whenever the DR bit of the LSR register goes high Note When both ETBEI 0 and ERBEI 0 the INT1 pin will stay in high impedance state with a 47k pullup connected to it 3 Li...

Page 69: ...H BD3 BD2 BD1 BD0 Read Write R W R W R W R W Initial Value 0 0 0 0 The BD3 BD0 bits form the Baud Rate divisor BD The resulting baud rate can be computed as Baudrate 115200 BD In the next table you can find the most typical values of BD BD Rate 0 disable baud generator 1 115 200 2 57600 3 38400 6 19200 12 9600 I 2 C The I2 C interface is provided for acceleration of operations with the I2 C EEPROM...

Page 70: ...ption of a byte from a slave 1 Transmit mode initial value the current transfer will be transmission to the slave This bit is set when the first byte after a START condition is written to the IDAR register It contains the state of the LSB bit of the first byte 2 Bus control register IBCR 7 6 5 4 3 2 1 0 Address CA H SCC MTS ACK INTE INT Read Write R W R W R W R W R W Initial Value 0 0 0 0 0 Bit 5 ...

Page 71: ... to 1 the INT3 interrupt is generated Bit 0 INT INTerrupt This is a transfer end interrupt request flag Write 0 To clear the flag write 0 to this bit until reading it will return 0 In the interrupt handler routine this must be done prior to any other operation of the I2C interface Otherwise the next Transfer End condition will be lost 1 Not applicable the flag is set and if the INTE bit is 1 the I...

Page 72: ...L E R The keyboard controller provides an interface to a standard PC AT keyboard When a key is pressed on the keyboard the controller receives a SCAN code of that key and stores it in the KBDR register Then it generates the interrupt INT2 The interrupt handling routine should buffer the SCAN codes and decode them Base Address EAH 1 Keyboard data register KBDR 7 6 5 4 3 2 1 0 Address EA H D7 D6 D5 ...

Page 73: ...ent is ON E g clearing bit 2 of the LEDDR1 register will switch the segment 2C on The segment annotation is standard F P G A E E P R O M The FPGA is configured from the AT17C256 serial configuration EEPROM memory everytime the power is applied to the board or the board is restarted by the Mainboard reset button To modify the content of the FPGA EEPROM the following steps must be done 1 On the main...

Page 74: ...f the tool please check the Processor Expert WWW site 1 FPGA EEPROM programming register This register is used by the FPGA EEPROM programming tool Its description here is included only for reference Please avoid writing to this register it can cause erasing of the FPGA EEPROM content and thus non functionality of the whole board FEPR 7 0 7 6 5 4 3 2 1 0 Address EF H SDAB SCLK B PEN Read Write R W ...

Page 75: ...of the mainboard System control DIP switches SW1 when the power is applied to the mainboard or mainboard Reset button is pressed the state of UMD0 2 FLASH8 16 SMALL and SWAP switches is copied to it ADR IO When 1 the A16 A23 CPU pins can be switched to general I O mode For description of this feature see the Mainboard User Reference chapter When 0 the A16 A23 pins are expected to behave as address...

Page 76: ... values from User Switches Status register after software reset CPU is set to mode defined by actual values of MD0 MD2 if MD0 MD2 are set to values defined for CPU Serial programming mode FPGA sets the logic levels on the CPU port P0 in the way that P00 and P01 pins of the CPU are pulled to 0 This invokes the asynchronous serial programming mode of the CPU Note if the FPGA detects that some of the...

Page 77: ...bank Int FLASH FF bank 0000BFH 000000H 0018FFH 000100H 003900H 002000H 00FFFFH 004000H Ext FLASH 256K 180000H 100000H FBFFFFH F80000H FEFFFFH FE0000H FFFFFFH FF0000H FPGA res FPGA res E00000H 2FFFFFH External bus mode with SWAP on Peripheral External FPGA Int RAM 6K External Peripheral Ext FLASH 256K 0000BFH 000000H 0018FFH 000100H 003900H 002000H 00FFFFH 004000H Ext RAM 512K 140000H 100000H FFFFF...

Page 78: ...ry can be accessed on lower addresses in the 2M block e g E00000H The Adr IO switch allows to use the A16 A23 CPU pins as a general I O mode pins If the switch is on any memory access above the 00FFFFh address is mirrored to the 4000h FFFFh area The decode logic FPGA ignores the A16 A23 address signals and the MirrorFF bit setting This switch allows to use the port P2 A16 A23 signals as general I ...

Page 79: ... the PE Help About dialog when the debugger is started 6 Mainboard version 7 6 5 4 3 2 1 0 Address C3H Mainboard version Read Write R For the Mainboard v 1 1 there is 11H in this register For the Mainboard v 1 2 there is 12H For the Mainboard v 1 3 there is 13H and so on Peripheral External FPGA Int RAM 6K External Peripheral Iimage of the area FF4000 FFFFFF Not Available 0000BFH 000000H 0018FFH 0...

Page 80: ... HBI and UKI see the Hardware Status register are log 1 the interrupt was caused by both pressing the User Key and the Hardware breakpoint Note only addresses A0 15 are compared when small model is selected System Configuration Register 8 Hardware Breakpoint Address Registers 7 6 5 4 3 2 1 0 Address C5H A7 A6 A5 A4 A3 A2 A1 A0 Read Write R W R W R W R W R W R W R W R W Initial Value 7 6 5 4 3 2 1 ...

Page 81: ...0 CPU signal stays in high impedance state with only 47k pullup connected to it Bit 2 UKI this bit can used to distinguish if the INT0 interrupt was caused by the User Key or the Hardware Breakpoint or both see Hardware Breakpoint Control register If UKI 1 the interrupt was caused by the User Key If both UKI and HBI see the Hardware Breakpoint Control register are log 1 the interrupt was caused by...

Page 82: ...80 80 80 80 Fig 2 The Mainboard layout with default jumper setting for Softune 1 2 3 4 5 6 7 8 ON ...

Page 83: ...N0 SOT0 signals are connected to the UART0 RS232 driver J22 3 4 5 6 The SIN1 SOT1 signals are connected to the UART1 RS232 driver J22 7 8 The UART0 1 Serial line reset is connected to the reset logic J23 3 4 5 6 The User UART SINU SOTU signals are connected to the User UART RS232 driver J23 7 8 The User UART Serial line reset is connected to the reset logic J23 11 12 13 14 The User UART CTSU RTSU ...

Page 84: ... contact our support 2 Switch MD0 to OFF and set the Serial programming mode on the Mainboard DIP switches Set all the jumpers to their default positions see the CPU and Mainboard layout figures and the J1 jumper to the 2 3 position Connect the serial cable to the USER UART port 3 Run the FlashTool Set the External bus free to yes and press Connect If you pass this step successfully it means that ...

Page 85: ...nnected properly on both sides Also close all programs that could possibly use the communication port you are trying to use 2 Check the serial line reset LED diodes D11 and D10 The D11 should shine until the debug session is started the D10 should be always OFF If this is not true check the configuration of J1 J2 jumpers J1 should be the 1 2 position J2 in the 2 3 position as displayed on the fig ...

Page 86: ... U P D A T E S For bug fixes in SW and HW please check this link www processorexpert com devkit16 Here you should find the most current versions of debug monitor kernel and also FPGA contents C H E C K T H E N E T F O R N E W E S T B E A N S You can download beans with extra feature on our website Just follow this link www processorexpert com devkit16 Professional Chapter 11 ...

Page 87: ...ard keyboard and VGA interface connected 650mA W E R E C O M M E N D U S I N G 9 V S T A B I L I Z E D P O W E R S U P P L Y W I T H 1 5 A M I N O U T P U T C U R R E N T I F T H E P O W E R S U P P L Y C A N N O T D E L I V E R C U R R E N T S A S S P E C I F I E D I N T H E S P E C I F I C A T I O N A B O V E T H E D E V K I T 1 6 W I L L N O T W O R K P R O P E R L Y T H E B O A R D W I L L B E...

Page 88: ...nts that the Product will perform substantially in accordance with the accompanying written materials for a period of 90 days form the date of receipt by the customer Concerning the hardware components of the Product Fujitsu Microelectronics Europe GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written mat...

Page 89: ...ed to intention and gross negligence NO LIABILITY FOR CONSEQUENTIAL DAMAGES To the maximum extent permitted by applicable law in no event shall Fujitsu Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever including but without limitation consequential and or indirect damages for personal injury assets of substantial value loss of profits interruption of business oper...

Page 90: ... K1 connectors pins on pages 86 87 88 was not consistent with the schematics Schematics bug on page 90 J11 was connected to SDA instead of SCL and J12 to SCL instead of SDA V1 22 15 02 2000 Points about burning Fujitsu debug monitor and PE debug kernel added to the paragraph Commonly used settings of the controls Chapter Flash It page 27 V1 23 16 02 2000 From the PE 2 34 version and higher or with...

Page 91: ...ning the Softune Workbench is recommended to be run first with the Demo LEDs project However the Softune PRJ file is generated by the PE during codesign process so the PE must be run first The paragraph was updated to reflect this change Also the communication settings for the Softune debug monitor are described there In the chapter 6 the section How to burn the CPU FLASH without Devkit16 was adde...

Page 92: ... 19 SCK0 86 AD01 P01 C1 20 SIN0 87 AD02 P02 A2 24 SOT1 88 AD03 P03 B2 22 SCK1 89 AD04 P04 C2 21 SIN1 90 AD05 P05 A3 91 AD06 P06 B3 92 AD07 P07 C3 93 AD08 P10 A4 69 INT0 94 AD09 P11 B4 70 INT1 95 AD10 P12 C4 71 INT2 96 AD11 P13 A5 72 INT3 97 AD12 P14 B5 29 INT4 98 AD13 P15 C5 30 INT5 99 AD14 P16 A6 31 INT6 100 AD15 P17 B6 32 INT7 1 A16 P20 C6 25 SOT2 2 A17 P21 A7 26 SCK2 3 A18 P22 B7 28 SIN2 4 A19 ...

Page 93: ...OUT2 IN6 SCL C15 60 OUT3 IN7 61 PPG0 P80 A16 65 OUT0 62 PPG1 P81 B16 66 OUT1 67 TIN1 P86 C16 VCC VCC A17 59 OUT3 IN7 33 ADTG P55 C17 60 OUT2 IN6 68 TOT1 P87 C17 AVCC 34 AVCC A18 35 AVR B18 36 AVR C18 AGND 37 AGND A19 38 AN0 P60 B19 39 AN1 P61 C19 GND GND GND C20 40 AN2 P62 A21 41 AN3 P63 C20 43 AN4 P64 A21 44 AN5 P65 B21 45 AN6 P66 C21 46 AN7 P67 A22 61 PPG0 77 RST B22 62 PPG1 52 HST C22 63 PPG2 6...

Page 94: ...tion CPU PIN Nr SIGNAL 2nd Function C26 59 OUT2 IN6 P76 A27 60 OUT3 IN7 P77 B27 NC SGO C27 NC SGA A28 73 TX0 P94 B28 74 RX0 P95 C28 75 TX1 P96 A29 76 RX1 P97 B29 79 X1AJ C29 80 X0AJ A30 82 X0J B30 83 X1J C30 VCC VCC A31 49 MD0 B31 50 MD1 C31 NC A32 51 MD2 B32 NC C32 GND GND ...

Page 95: ...EADER15X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 K5 HEADER15X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 K4 HEADER10X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 K6 HEADER10X2 A16 A18 A20 A22 ALE GND WRH HAK CLK SCK0 SIN1 FVCC SOT2 C INT4 INT6 ADTG AVR AGND AN1 AN3 AN4 AN6 TIN0 MD0 A17 A19 A21 A23 RD WRL HRQ RDY SOT0 SIN0 SCK1 SOT1 SCK2 SI...

Page 96: ...CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 K8 HEADER8X2 AVCC AGND AN6 AVR ADTG AN0 AN2 AVCC AN5 AN7 AVR AVR AN1 AN3 AN4 AGND AD Header SER 0 8 SINU SOTU UARTSW 0 1 CTSU RTSU Serial_IF Serial_IF sch SER 0 8 SINU SOTU UARTSW 0 1 CTSU RTSU RX1 TX1 RX0 TX0 AudioIn CAN_Sound CAN_Snd sch RX1 TX1 RX0 TX0 AudioIn AD 0 15 A 16 23 BusCtrl 0 7 Addr_IO CSRAM 0 1 CSFLASH BYTE AD15 A00 RY BY Memories Memories sc...

Page 97: ... IC13 MAX232A GND GND GND C26 100n C27 100n C28 100n C29 100n C30 100n C1 1 C1 3 C2 4 C2 5 V 2 V 6 T1OUT 14 T2OUT 7 R1IN 13 R2IN 8 T1IN 11 T2IN 10 R1OUT 12 R2OUT 9 VCC 16 GND 15 IC14 MAX232A GND GND GND C31 100n C32 100n C33 100n C34 100n C35 100n C1 1 C1 3 C2 4 C2 5 V 2 V 6 T1OUT 14 T2OUT 7 R1IN 13 R2IN 8 T1IN 11 T2IN 10 R1OUT 12 R2OUT 9 VCC 16 GND 15 IC15 MAX232A GND GND GND SOT0D 1 2 3 4 5 6 7 ...

Page 98: ...3 IO194 194 IO196 196 IO197 197 IO198 198 IO199 199 IO200 200 IO201 201 IO204 204 IO205 205 IO206 206 GND 1 GND 13 GND 25 GND 38 GND 51 GND 66 GND 79 GND 91 GND 103 GND 118 GND 131 GND 143 GND 158 GND 170 GND 182 GND 195 VCC 208 VCC 26 VCC 53 VCC 78 VCC 105 VCC 130 VCC 156 VCC 183 IC6 XCS20 4 TQ 208 C AD15 A00 AD07 AD00 AD01 AD06 AD02 AD05 AD03 AD04 SP37 SP36 SP35 SP34 SP33 SP32 SP31 SP30 SP27 SP2...

Page 99: ...23 1k R24 1k R25 1k R26 1k R27 1k R28 1k VCC VCC CSLED0 CSLED1 GND GND DI2A DI2B DI2C DI2D DI2E DI2F DI2G DI2H DI1A DI1B DI1C DI1D DI1E DI1F DI1G DI1H OC 1 C 11 D1 2 Q1 19 D2 3 Q2 18 D3 4 Q3 17 D4 5 Q4 16 D5 6 Q5 15 D6 7 Q6 14 D7 8 Q7 13 D8 9 Q8 12 IC16 74HCT573M OC 1 C 11 D1 2 Q1 19 D2 3 Q2 18 D3 4 Q3 17 D4 5 Q4 16 D5 6 Q5 15 D6 7 Q6 14 D7 8 Q7 13 D8 9 Q8 12 IC17 74HCT573M LED Display R19 10k R29...

Page 100: ...Kit16 Mainboard Memories Ver 1 3 A01 A03 A02 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16M AD01 AD03 AD05 AD07 AD06 AD04 AD02 AD00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16M AD01 AD03 AD05 AD07 AD06 AD04 AD02 AD00 GND GND VCC VCC A01 A03 A02 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16M AD10 AD09 AD08 AD15 AD14 AD13 AD12 AD11 A01 A02 A03 A04 A05 A06 A07 A08 A09 ...

Page 101: ...8 3 7 2 6 1 K3 CAN 9 V 90 1 2 3 4 5 6 7 8 9 10 J25 HEADER5X2 1 2 3 4 5 6 7 8 9 10 J24 HEADER5X2 VCC VCC VCC VCC GND GND GND GND GND VCC TX0 RX0 TX1 RX1 P4 47K P3 47K GND GND 1 J26 JUMPER2 1 J27 JUMPER2 INT5 INT4 1 2 3 IC24A 74HCT32 1 J28 JUMPER2 INT4 P1 10K GND SP1 KPB1220 2 3 G 4 V 6 1 8 B 7 5 IC22 LM386 R60 10K C60 4K7 GND GND C62 50K R62 10 GND C63 250uF 10V 1 J17 JUMPER2 GND 1 2 K16 HEADER2 GN...

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