77
77
77
77
pins than the CPU would provide with all the external bus pins used. The
memory map for the Adr/IO switch ON mode is shown on the following figure:
(5) FPGA content version
7
6
5
4
3
2
1
0
Address:C2
H
Xilinx content version
Read/Write
(R)
The FPGA content version can be found in the PE "Help - About" dialog, when
the debugger is started.
(6) Mainboard version
7
6
5
4
3
2
1
0
Address:C3
H
Mainboard version
Read/Write
(R)
•
For the Mainboard v. 1.1, there is 11H in this register.
•
For the Mainboard v. 1.2, there is 12H.
•
For the Mainboard v. 1.3, there is 13H, and so on.
Peripheral
External-FPGA
Int. RAM
6K
External
Peripheral
Iimage of the area
FF4000-FFFFFF
Not Available
0000BFH
000000H
0018FFH
000100H
003900H
002000H
00FFFFH
004000H
100000H
FFFFFFH
External bus mode with Adr/IO on
