65
65
65
65
Output mode
Read
: The level at the corresponding pin is read. In most cases it will be the
value written to the pin as last, the only exception can happen when the
pin is erroneously pulled hard to VCC or GND.
Write
: Data is written to an output latch and output to the corresponding pin.
(2) Port direction registers
DDR4
7
6
5
4
3
2
1
0
Initial
value
Access
Address: E4
H
D07
D06
D05
D04
D03
D02
D01
D00
00
H
W
DDR5
15
14
13
12
11
10
9
8
Initial
value
Access
Address: E5
H
D17
D16
D15
D14
D13
D12
D11
D10
00
H
W
DDR6
7
6
5
4
3
2
1
0
Initial
value
Access
Address:E6
H
D27
D26
D25
D24
D23
D22
D21
D20
00
H
W
DDR7
15
14
13
12
11
10
9
8
Initial
value
Access
AE7
H
D37
D36
D35
D34
D33
D32
D31
D30
00
H
W
When reading the register, last value written to it is returned.
Pins are controlled as described below:
0
: Input mode
1
: Output mode
Note: The port direction registers are WRITE ONLY. Pull-up resistors
47K are internally connected to port pins.
U S E R U A R T
The User UART has the ”mimic” of a simplified 16550C serial
asynchronous UART. The main differences are:
•
received and transmitted data are double buffered, not FIFOed in 16
bytes long buffer
•
only basic serial stream mode is provided (1 start, 8 data bits, 1 stop bit)
•
Send Break and Break Indicate functions supported
•
the number of baud rates is limited to 16
•
Hardware flow control CTS, RTS signals are used by default
•
no DSR, DTR signals
