Fujitsu DevKit16, User Manual

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DDR3 15 14 13 12 11 10 9 8 Initial
value
Acces
s
Addr.: DF
H
D37 D36 D35 D34 D33 D32 D31 D30 00
H
R/W
When reading the register, last value written to it is returned.
Pins are controlled as described below:
0 = Input mode
1 = Output mode
Note: Pull-up resistors 47K are internally connected to port pins.
A D D - O N F P G A P O R T S
These ports are provided with FPGA content version 1 and can be found on
FPGA User Programmable Pins connector.
Registers
Base Address: 0000E0
H
(1) Port data registers
PDR4 7 6 5 4 3 2 1 0 Initial
value
Access
Address:E0
H
P07 P06 P05 P04 P03 P02 P01 P00 00
H
R/W
PDR5 15 14 13 12 11 10 9 8 Initial
value
Access
Address: E1
H
P17 P16 P15 P14 P13 P12 P11 P10 00
H
R/W
PDR6 7 6 5 4 3 2 1 0 Initial
value
Access
Address: E2
H
P27 P26 P25 P24 P23 P22 P21 P20 00
H
R/W
PDR7 15 14 13 12 11 10 9 8 Initial
value
Access
Address: E3
H
P37 P36 P35 P34 P33 P32 P31 P30 00
H
R/W