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The Mainboard
Programmer‘s Reference
This section describes internal registers of the FPGA chip, which provides the
biggest portion of the Mainboard functionality. The FPGA is connected to the
CPU external bus, so it is necessary to program all the CPU external bus pins
(including the CLK and /WRL pins) to the external bus mode with the 8-bit
access to the 0C0H-0FFH area. In Processor Expert environment, this is done
automatically when using any of the “MB90540 external bus” project templates.
R E G I S T E R A D D R E S S E S A N D C H I P S E L E C T S
FPGA I/O space is mapped to CPU bank 0 and starts from 0C0H
System Control Registers:
0C0H – 0C8H
I
2
C:
0C9H – 0CFH
UART:
0D0H – 0D3H
Add-on FPGA output only port:
0D7H
Simulated CPU ports:
0D8H – 0DFH
Add-on FPGA ports:
0E0H – 0E7H
Keyboard Controller:
0EAH, 0EBH
FPGA EEPROM :
0EFH
WWLED:
0E8H, 0E9H
CSUSERIO
*
:
0F0H – 0FFH
*The CSUSERIO signal is generated by the FPGA when accessing this area. It is provided on the
Prototype connector.
I N T E R R U P T S
The interrupts in the following table are used by the Mainboard and should not
be used by an user harware:
INT0
Hardware breakpoint, User Key Button
INT1
User (FPGA) UART
INT2
Keyboard
INT3
FPGA I
2
C
Chapter
9
Chapter
9
