69
69
69
69
[Bit 4]
MS:
Master Transfer Start
This bit controls I
2
C data transfer.
0:
The stop condition is generated and address data transfer terminated.
1:
The start condition is generated and address data transfer started.
[Bit 3]
ACK:
Acknowledge
This bit enables acknowledge generation when data is received.
•
Write
0:
Acknowledge is not generated.
1:
Acknowledge is generated.
[Bit 1]
INTE:
INTEnable
This bit enables the INT3 interrupt generation after a transfer is terminated.
0:
the interrupt is disabled (initial value), the INT3 pin stays in the high
impedance state with 47k pullup.
1:
the interrupt is enabled - when the INT bit goes to '1', the INT3 interrupt
is generated
[Bit 0]
INT:
INTerrupt
This is a transfer end interrupt request flag.
•
Write
0
: To clear the flag, write '0' to this bit until reading it will return '0'. In
the interrupt handler routine, this must be done prior to any other
operation of the I2C interface. Otherwise, the next Transfer End
condition will be lost.
1
: Not applicable (the flag is set, and if the INTE bit is '1', the INT3
interrupt is generated)
•
Read
0
: The transfer is not terminated
1
: This bit is set when an one-byte transfer (including the acknowledge
bit) is terminated.
(3) Clock control register
ICCR
7
6
5
4
3
2
1
0
Address: CB
H
---
---
---
---
CS3
CS2
CS1
CS0
Read/Write
(---)
(---)
(---)
(---)
(R/W)
(R/W)
(R/W)
(R/W)
Initial Value
(---)
(---)
(---)
(---)
(X)
(X)
(X)
(X)
The value of CS3-CS0 bits of this register form a divider of the base I
2
C
clock - 384 kHz. The resulting SCL clock frequency can be then computed
as:
